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PDF 100344PC Data sheet ( Hoja de datos )
| Número de pieza | 100344PC | |
| Descripción | Low Power 8-Bit Latch with Cut-Off Drivers | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 1988
Revised August 2000
100344
Low Power 8-Bit Latch with Cut-Off Drivers
General Description
The 100344 contains eight D-type latches, individual inputs
(Dn), outputs (Qn), a common enable pin (E), latch enable
(LE), and output enable pin (OEN). A Q output follows its D
input when both E and LE are LOW. When either E or LE
(or both) are HIGH, a latch stores the last valid data
present on its D input prior to E or LE going HIGH.
A HIGH on OEN holds the outputs in a cut-off state. The
cut-off state is designed to be more negative than a normal
ECL LOW level. This allows the output emitter-followers to
turn off when the termination supply is −2.0V, presenting a
high impedance to the data bus. This high impedance
reduces termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100344 outputs are designed to drive a doubly termi-
nated 50Ω transmission line (25Ω load impedance). All
inputs have 50 kΩ pull-down resistors.
Features
s Cut-off drivers
s Drives 25Ω load
s Low power operation
s 2000V ESD protection
s Voltage compensated operating range = −4.2V to −5.7V
Ordering Code:
Order Number Package Number
Package Description
100344PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100344QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100344QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Logic Symbol
© 2000 Fairchild Semiconductor Corporation DS009883
www.fairchildsemi.com
1 page  
Test Circuitry
Note:
• VCC, VCCA = +2V, VEE = −2.5V
• L1 and L2 = equal length 50Ω impedance lines
• RT = 50Ω terminator internal to scope
• Decoupling 0.1 µF from GND to VCC and VEE
• All unused outputs are loaded with 25Ω to GND
• CL = Fixture and stray capacitance ≤ 3 pF
Switching Waveforms
FIGURE 1. AC Test Circuit
FIGURE 2. Propagation Delay and Cutoff Times
FIGURE 3. Setup, Hold and Pulse Width Times
FIGURE 4. Propagation Delay LE, E to Q
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 100344PC.PDF ] | |
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