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PDF 30141-23 Data sheet ( Hoja de datos )

Número de pieza 30141-23
Descripción Geode GXm Processor Integrated x86 Solution with MMX Support
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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April 2000
Geode™ GXm Processor
Integrated x86 Solution with MMX Support
General Description
The National Semiconductor® Geode™ GXm processor
is an advanced 32-bit x86 compatible processor offering
high performance, fully accelerated 2D graphics, a 64-bit
synchronous DRAM controller and a PCI bus controller,
all on a single chip that is compatible with Intel’s MMX
technology.
The GXm processor core is a proven design that offers
competitive CPU performance. It has integer and floating
point execution units that are based on sixth-generation
technology. The integer core contains a single, six-stage
execution pipeline and offers advanced features such as
operand forwarding, branch target buffers, and extensive
write buffering. A 16 KB write-back L1 cache is accessed
in a unique fashion that eliminates pipeline stalls to fetch
operands that hit in the cache.
In addition to the advanced CPU features, the GXm pro-
cessor integrates a host of functions which are typically
implemented with external components. A full-function
graphics accelerator provides pixel processing and ren-
dering functions.
A separate on-chip video buffer enables >30 fps MPEG1
video playback when used together with the CS5530 I/O
companion chip. Graphics and system memory accesses
are supported by a tightly-coupled synchronous DRAM
(SDRAM) memory controller. This tightly coupled memory
subsystem eliminates the need for an external L2 cache.
The GXm processor includes Virtual System Architec-
ture® (VSA™ technology) enabling XpressGRAPHICS
and XpressAUDIO subsystems as well as generic emula-
tion capabilities. Software handler routines for the Xpress-
GRAPHICS and XpressAUDIO subsystems can be
included in the BIOS and provide compatible VGA and 16-
bit industry standard audio emulation. XpressAUDIO tech-
nology eliminates much of the hardware traditionally asso-
ciated with audio functions.
Geode™ GXm Processor Internal Block Diagram
Write-Back
Cache Unit
C-Bus
MMU
Integer
Unit
Internal Bus Interface Unit
X-Bus
FPU
Integrated
Functions
Graphics
Pipeline
Memory
Controller
Display
Controller
PCI
Controller
SDRAM Port
CS5530
(CRT/LCD TFT)
PCI Bus
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
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30141-23 pdf
Table of Contents (Continued)
4.3 MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.3.1 Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3.2 Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3.3 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3.4 Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.5 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.6 Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.3.7 SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.4 GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.4.1 BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.4.2 Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.4.3 Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.4.4 Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.4.5 Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.4.6 Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5 DISPLAY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.5.1 Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.5.2 Compression Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.5.3 Motion Video Acceleration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.5.4 Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.5.5 Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.5.6 Dither and Frame-Rate Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.5.7 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.5.8 Graphics Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.5.9 Display Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.5.10 Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
4.5.11 Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
4.5.12 Cursor Position Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.5.13 Color Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.5.14 Palette Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.5.15 CS5530 Display Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.6 PCI CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6.1 X-Bus PCI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6.2 X-Bus PCI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6.3 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6.4 Generating Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6.5 Generating Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6.6 PCI Configuration Space Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
4.6.7 PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.6.8 PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.0 Virtual Subsystem Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.1 VIRTUAL VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.1.1 Traditional VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2 GXM VIRTUAL VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Datapath Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Video Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
GXm VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
VGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Virtual VGA Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Revision 3.1
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30141-23 arduino
Architecture Overview (Continued)
1.6 GEODE GXM/CS5530 SYSTEM DESIGNS
The GXm Integrated Subsystem with MMX support con-
sists of two chips, the GXm Processor and the CS5530
I/O companion. The subsystem provides high perfor-
mance using 32-bit x86 processing. The two chips inte-
grate video, audio and memory interface functions
normally performed by external hardware.
As described in separate manuals, the CS5530 enables
the full features of the GXm processor with MMX support.
These features include full VGA and VESA video, 16-bit
stereo sound, IDE interface, ISA interface, SMM power
management, and AT compatibility logic. In addition, the
newer CS5530 provides an Ultra DMA/33 interface,
MPEG2 assist, and AC97 Version 2.0 compliant audio.
Figure 1-2 shows a basic block system diagram (refer to
Figure 2-4 on page 34 for detailed subsystem intercon-
nection signals). It includes the National Semiconductor
CS9210 Dual-Scan Flat Panel Display Controller for
designs that need to interface to a DSTN panel (instead of
TFT panel).
SDRAM
USB
(2 Ports)
Speakers
CD
ROM
Audio
AC97
Codec
Micro-
phone
GPIO
MD[63:0]
SDRAM
Port
YUV Port
(Video)
Clocks
System
Clocks
Geode™ CS5530
I/O Companion
Geode™ GXm
Processor
Serial
Packet
RGB Port
(Graphics)
PCI Interface
CRT
PCI Bus
Graphics Data
Video Data
Analog RGB
Digital RGB (to TFT or DSTN Panel)
TFT
Panel
IDE Control
14.31818
MHz Crystal
Super
I/O
BIOS
IDE
Devices
Geode™
CS9210
DSTN
Controller
DC-DC & Battery
ISA Bus
DSTN Panel
Figure 1-2. Geode™ GXm/CS5530 System Block Diagram
Revision 3.1
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