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PDF 100341 Data sheet ( Hoja de datos )

Número de pieza 100341
Descripción Low Power 8-Bit Shift Register
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 100341 Hoja de datos, Descripción, Manual

July 1988
Revised August 2000
100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (Pn) and outputs (Qn) for parallel
operation, and with serial inputs (Dn) and steering logic for
bidirectional shifting. The flip-flops accept input data a
setup time before the positive-going transition of the clock
pulse and their outputs respond a propagation delay after
this rising clock edge.
The circuit operating mode is determined by the Select
inputs S0 and S1, which are internally decoded to select
either “parallel entry”, “hold”, “shift left” or “shift right” as
described in the Truth Table. All inputs have 50 kpull-
down resistors.
Features
s 35% power reduction of the 100141
s 2000V ESD protection
s Pin/function compatible with 100141
s Voltage compensated operating range = −4.2V to 5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
10034SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100341PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100341QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100341QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
Description
CP Clock Input
S0, S1
D0, D7
P0P7
Q0Q7
Select Inputs
Serial Inputs
Parallel Inputs
Data Outputs
© 2000 Fairchild Semiconductor Corporation DS009880
28-Pin PLCC
www.fairchildsemi.com

1 page




100341 pdf
Industrial Version
PLCC DC Electrical Characteristics (Note 7)
VEE = −4.2V to 5.7V, VCC = VCCA = GND, TC = −40°C to +85°C
Symbol
Parameter
TC = −40°C
Min Max
TC = 0°C to +85°C
Min Max
Units
Conditions
VOH
VOL
VOHC
VOLC
VIH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
1085
1830
1095
1170
870
1575
1565
870
1025
1830
1035
1165
870
1620
1610
870
mV VIN = VIH(Max)
Loading with
mV or VIL (Min)
50to 2.0V
mV VIN = VIH (Min)
Loading with
mV or VIL (Max)
50to 2.0V
mV Guaranteed HIGH Signal
for all Inputs
VIL Input LOW Voltage
1830 1480 1830 1475
mV Guaranteed LOW Signal
for all Inputs
IIL Input LOW Current
0.50
0.50
µA VIN = VIL (Min)
IIH Input HIGH Current
240 240 µA VIN = VIH (Max)
IEE Power Supply Current
Inputs OPEN
157 75 157 75
mA VEE = −4.2V to 4.8V
167 75 167 75
mA VEE = −4.2V to 5.7V
Note 7: The specified limits represent the worst casevalue for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under worst caseconditions.
PLCC AC Electrical Characteristics
VEE = −4.2V to 5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −40°C
Min Max
TC = +25°C
Min Max
TC = +85°C
Min Max
Units
Conditions
fMAX
Max Clock Frequency
425 425 425 MHz Figures 2, 3
tPLH Propagation Delay
tPHL CP to Output
0.90
1.80
1.00
1.80
1.00
1.90
Figures 1, 3
ns
(Note 8)
tTLH Transition Time
tTHL 20% to 80%, 80% to 20%
0.30
1.90
0.35
1.20
0.35
1.20
ns Figures 1, 3
tS Setup Time
Dn, Pn
0.60
0.55
0.55
ns
Sn 1.70 1.50 1.50
tH Hold Time
Dn, Pn
0.90
0.70
0.70
Figure 4
ns
Sn 0.50 0.50 0.50
tPW(H)
Pulse Width HIGH
CP
2.00
2.00
2.00
ns Figure 3
Note 8: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
5 www.fairchildsemi.com

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