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PDF 100336PC Data sheet ( Hoja de datos )
| Número de pieza | 100336PC | |
| Descripción | Low Power 4-Stage Counter/Shift Register | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1989
Revised August 2000
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down
counter or as a 4-bit bidirectional shift register. Three
Select (Sn) inputs determine the mode of operation, as
shown in the Function Select table. Two Count Enable
(CEP, CET) inputs are provided for ease of cascading in
multistage counters. One Count Enable (CET) input also
doubles as a Serial Data (D0) input for shift-up operation.
For shift-down operation, D3 is the Serial Data input. In
counting operations the Terminal Count (TC) output goes
LOW when the counter reaches 15 in the count/up mode or
0 (zero) in the count/down mode. In the shift modes, the TC
output repeats the Q3 output. The dual nature of this TC/Q3
output and the D0/CET input means that one interconnec-
tion from one stage to the next higher stage serves as the
link for multistage counting or shift-up operation. The indi-
vidual Preset (Pn) inputs are used to enter data in parallel
or to preset the counter in programmable counter applica-
tions. A HIGH signal on the Master Reset (MR) input over-
rides all other inputs and asynchronously clears the flip-
flops. In addition, a synchronous clear is provided, as well
as a complement function which synchronously inverts the
contents of the flip-flops. All inputs have 50 kΩ pull-down
resistors.
Features
s 40% power reduction of the 100136
s 2000V ESD protection
s Pin/function compatible with 100136
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100336SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100336PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100336QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100336QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Logic Symbol
© 2000 Fairchild Semiconductor Corporation DS010584
www.fairchildsemi.com
1 page  
Commercial Version (Continued)
DIP AC Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = 0°C
Min Max
TC = +25°C
Min Max
TC = +85°C
Min Max
Units
Conditions
fSHIFT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Shift Frequency
Propagation Delay
CP to Qn, Qn
Propagation Delay
CP to TC (Shift)
Propagation Delay
CP to TC (Count)
Propagation Delay
MR to Qn, Qn
Propagation Delay
MR to TC (Count)
Propagation Delay
MR to TC (Shift)
300
1.00
2.10
2.40
1.40
2.80
2.40
2.00
3.50
4.40
2.50
5.10
4.00
300
1.00
2.10
2.40
1.40
2.90
2.40
2.00
3.50
4.40
2.50
5.20
4.00
300
1.00
2.10
2.60
1.50
3.10
2.50
2.00
3.70
4.70
2.60
5.50
4.10
MHz
ns
ns
ns
ns
ns
ns
Figures 2, 3
Figures 1, 3
(Note 5)
Figures 1, 7, 8
(Note 5)
Figures 1, 9
(Note 5)
Figures 1, 4
(Note 5)
Figures 1, 12
(Note 5)
Figures 1, 10, 11
(Note 5)
tPLH Propagation Delay
tPHL D0/CET to TC
1.80
3.10
1.80
3.10
1.90
3.30
ns
Figures 1, 5
tPLH Propagation Delay
tPHL
Sn to TC
1.90
4.10
1.90
4.10
2.10
4.40
(Note 5)
ns
tTLH Transition Time
0.35
1.20
0.35
1.20
0.35
1.20
ns Figures 1, 3
tTHL 20% to 80%, 80% to 20%
tS Setup Time
D3
1.00
1.00
1.00
Pn
1.50
1.50
1.50
D0/CET
CEP
1.30
1.40
1.30
1.40
1.30
1.40
ns Figures 6, 4
Sn
3.40
3.40
3.40
MR (Release Time)
2.60
2.60
2.60
tH Hold Time
D3
Pn
D0/CET
CEP
0.40
0.30
0.30
0.20
0.40
0.30
0.30
0.20
0.40
0.30
0.30
0.20
ns Figure 6
tPW(H)
Sn
Pulse Width HIGH
CP, MR
0.10
2.00
0.10
2.00
0.10
2.00
ns Figures 3, 4
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
5 www.fairchildsemi.com
5 Page 
Switching Waveforms (Continued)
Note:
*Decimal representation of binary outputs.
Count Up: S0 = L, S1 = H, S2 = H; Count Down: S0 = L, S1 = L, S2 = H.
Measurement taken at 50% point of waveform.
FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes)
Note: Shift Right Mode; S0 = H, S1 = H, S2 = L.
FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode)
Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.
FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode)
Note:
*Decimal representation of binary outputs. Count Up Mode: S0 = L, S1 = H, S2 = H.
Note:
*Decimal representation of binary outputs. Count Down Mode: S0 = L, S1 = L, S2 = H.
FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes)
11 www.fairchildsemi.com
11 Page | ||
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| PDF Descargar | [ Datasheet 100336PC.PDF ] | |
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