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PDF 100336F Data sheet ( Hoja de datos )
| Número de pieza | 100336F | |
| Descripción | Low Power 4-Stage Counter/Shift Register | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1998
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down
counter or as a 4-bit bidirectional shift register. Three Select
(Sn) inputs determine the mode of operation, as shown in the
Function Select table. Two Count Enable (CEP, CET) inputs
are provided for ease of cascading in multistage counters.
One Count Enable (CET) input also doubles as a Serial Data
(D0) input for shift-up operation. For shift-down operation, D3
is the Serial Data input. In counting operations the Terminal
Count (TC) output goes LOW when the counter reaches 15
in the count/up mode or 0 (zero) in the count/down mode. In
the shift modes, the TC output repeats the Q3 output. The
dual nature of this TC/Q3 output and the D0/CET input
means that one interconnection from one stage to the next
higher stage serves as the link for multistage counting or
shift-up operation. The individual Preset (Pn) inputs are used
to enter data in parallel or to preset the counter in program-
mable counter applications. A HIGH signal on the Master Re-
set (MR) input overrides all other inputs and asynchronously
clears the flip-flops. In addition, a synchronous clear is pro-
vided, as well as a complement function which synchro-
nously inverts the contents of the flip-flops. All inputs have 50
kΩ pull-down resistors.
Features
n 40% power reduction of the 100136
n 2000V ESD protection
n Pin/function compatible with 100136
n Voltage compensated operating range = −4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9230601
Logic Symbol
DS100307-1
Pin
Names
CP
CEP
D0/CET
S0– S2
MR
P0– P3
D3
TC
Q0– Q3
Q0– Q3
Description
Clock Pulse Input
Count Enable Parallel Input (Active LOW)
Serial Data Input/Count Enable
Trickle Input (Active LOW)
Select Inputs
Master Reset Input
Preset Inputs
Serial Data Input
Terminal Count Output
Data Outputs
Complementary Data Outputs
© 1998 National Semiconductor Corporation DS100307
www.national.com
1 page  
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature (TSTG)
Maximum Junction Temperature (TJ)
Ceramic
VEE Pin Potential to Ground Pin
Input Voltage (DC)
Output Current (DC Output HIGH)
ESD (Note 3)
−65˚C to +150˚C
+175˚C
−7.0V to +0.5V
VEE to +0.5V
−50 mA
≥2000V
Recommended Operating
Conditions
Case Temperature (TC)
Military
−55˚C to +125˚C
Supply Voltage (VEE)
−5.7V to −4.2V
Note 2: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, T C = −55˚C to +125˚C
Symbol
Parameter
Min Max Units
VOH Output HIGH Voltage −1025 −870 mV
TC
0˚C to
+125˚C
−1085 −870 mV −55˚C
VOL Output LOW Voltage −1830 −1620 mV 0˚C to
+125˚C
Conditions
VIN = VIH (Max) Loading with
or VIL (Min)
50Ω to −2.0V
Notes
(Notes 4, 5, 6)
−1830 −1555 mV −55˚C
VOHC
VOLC
Output HIGH Voltage −1035
mV
−1085
mV
Output LOW Voltage
−1610 mV
0˚C to
+125˚C
−55˚C
0˚C to
+125˚C
VIN = VIH (Min)
or VIL (Max)
Loading with
50Ω to −2.0V
(Notes 4, 5, 6)
−1555 mV −55˚C
VIH Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal
+125˚C for All Inputs
(Notes 4, 5, 6, 7)
VIL Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal
+125˚C for All Inputs
(Notes 4, 5, 6, 7)
IIL
Input LOW Current
0.50
µA −55˚C to VEE = −4.2V
+125˚C VIN = VIL (Min)
IIH Input HIGH Current
240 µA
0˚C to VEE = −5.7V
+125˚C VIN = VIH(Max)
340 µA
−55˚C
(Notes 4, 5, 6)
(Notes 4, 5, 6)
IEE Power Supply Current
−55˚C Inputs Open
−185 −70 mA
to VEE = −4.2V to −4.8V
−195 −70
+125˚C VEE = −4.2V to −5.7V
(Notes 4, 5, 6)
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 5: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 7: Guaranteed by applying specified input conditon and testing VOH/VOL.
5 www.national.com
5 Page 
Switching Waveforms (Continued)
DS100307-17
Note:
*Decimal representation of binary outputs.
Count Up: S0 = L, S1 = H, S2 = H; Count Down: S0 = L, S 1 = L, S2 = H.
Measurement taken at 50% point of waveform.
FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes)
DS100307-18
Note: Shift Right Mode; S0 = H, S1 = H, S2 = L.
FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode)
DS100307-19
Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.
FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode)
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 100336F.PDF ] | |
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