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PDF 100331SC Data sheet ( Hoja de datos )

Número de pieza 100331SC
Descripción Low Power Triple D-Type Flip-Flop
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 100331SC Hoja de datos, Descripción, Manual

February 1990
Revised August 2000
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CPC), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CPn),
Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters
a master when both CPn and CPC are LOW and transfers
to a slave when CPn or CPC (or both) go HIGH. The Master
Set, Master Reset and individual CDn and SDn inputs over-
ride the Clock inputs. All inputs have 50 kpull-down
resistors.
Features
s 35% power reduction of the 100131
s 2000V ESD protection
s Pin/function compatible with 100131
s Voltage compensated operating range = −4.2V to 5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100331SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100331PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100331QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100331QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
CP0CP2
CPC
D0D2
CD0CD2
SDn
MR
MS
Q0-Q2
Q0Q2
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010262
28-Pin PLCC
www.fairchildsemi.com

1 page




100331SC pdf
Commercial Version (Continued)
Symbol
Parameter
TC = 0°C
Min Max
TC = +25°C
Min Max
TC = +85°C
Min Max
Units
Conditions
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tOSHL
Propagation Delay
CPC to Output
Propagation Delay
CPn to Output
Propagation Delay
CDn, SDn to Output
Propagation Delay
MS, MR to Output
Maximum Skew Common Edge
Output-to-Output Variation
0.75 1.40 0.75 1.40 0.80 1.50
0.70 1.40 0.75 1.40 0.80 1.50
0.70 1.50 0.70 1.50 0.80 1.60
0.80 1.70 0.80 1.70 0.80 1.80
1.10 2.00 1.10 2.00 1.20 2.10
1.20 2.10 1.20 2.10 1.30 2.20
100 100 100
ns
Figures 1, 3 PLCC Only
ns
CPn, CPC =L
PLCC Only
ns
CPn, CPC = H
PLCC Only
CPn, CPC = L
PLCC Only
ns
CPn, CPC = H
PLCC Only
PLCC Only
ps (Note 4)
Figures 1, 4
Common Clock to Output Path
tOSHL
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
235 235 235 ps (Note 4)
tOSLH
CPn to Output Path
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
120 120 120 ps (Note 4)
Common Clock to Output Path
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
275 275 275 ps (Note 4)
CPn to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
ps PLCC Only
125 125 125 (Note 4)
Common Clock to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
ps PLCC Only
265 265 265 (Note 4)
CPn to Output Path
tPS Maximum Skew
PLCC Only
Pin (Signal) Transition Variation 90 90 90 ps (Note 4)
Common Clock to Output Path
tPS Maximum Skew
PLCC Only
Pin (Signal) Transition Variation 90 90 90 ps (Note 4)
CPn to Output Path
Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
5 www.fairchildsemi.com

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