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PDF 100328QI Data sheet ( Hoja de datos )
| Número de pieza | 100328QI | |
| Descripción | Low Power Octal ECL/TTL Bi-Directional Translator with Latch | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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April 1989
Revised August 2000
100328
Low Power Octal ECL/TTL Bi-Directional Translator
with Latch
General Description
The 100328 is an octal latched bi-directional translator
designed to convert TTL logic levels to 100K ECL logic lev-
els and vice versa. The direction of this translation is deter-
mined by the DIR input. A LOW on the output enable input
(OE) holds the ECL outputs in a cut-off state and the TTL
outputs at a high impedance level. A HIGH on the latch
enable input (LE) latches the data at both inputs even
though only one output is enabled at the time. A LOW on
LE makes the 100328 transparent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is −2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100328 is designed with FAST TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All inputs have
50 kΩ pull-down resistors.
Features
s Identical performance to the 100128 at 50% of the
supply current
s Bi-directional translation
s 2000V ESD protection
s Latched outputs
s FAST TTL outputs
s 3-STATE outputs
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
Ordering Code:
Order Number Package Number
Package Description
100328SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100328PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100328QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100328QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
E0–E7
T0–T7
OE
ECL Data I/O
TTL Data I/O
Output Enable Input
LE Latch Enable Input
DIR Direction Control Input
All pins function at 100K ECL levels except for T0–T7.
FAST is a registered trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010219
www.fairchildsemi.com
1 page  
Commercial Version (Continued)
DIP ECL-to-TTL AC Electrical Characteristics
VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF
Symbol
Parameter
TC = 0°C
Min Max
TC = 25°C
Min Max
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSET
tHOLD
tPW(H)
En to Tn
(Transparent)
LE to Tn
OE to Tn
(Enable Time)
OE to Tn
(Disable Time)
DIR to Tn
(Disable Time)
En to LE
En to LE
Pulse Width LE
2.3 5.6 2.4 5.6
3.1 7.2 3.1 7.2
3.4 8.45 3.7 8.95
3.8 9.2 4.0 9.2
3.2 8.95 3.3 8.95
3.0 7.7 3.4 8.7
2.7 8.2 2.8 8.7
2.8 7.45 3.1 7.95
1.1 1.1
2.1 2.1
4.1 4.1
TC = 85°C
Min Max
2.6 5.9
3.3 7.7
4.0 9.7
4.3 9.95
3.5 9.2
4.1 9.95
3.1 8.95
4.0 9.2
1.1
2.6
4.1
Units
Conditions
ns Figures 3, 4
ns Figures 3, 4
ns Figures 3, 5
ns Figures 3, 5
ns Figures 3, 6
ns Figures 3, 6
ns Figures 3, 4
ns Figures 3, 7
SOIC and PLCC TTL-to-ECL AC Electrical Characteristics
VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V
Symbol
Parameter
TC = 0°C
Min Max
TC = 25°C
Min Max
TC = 85°C
Min Max
Units
Conditions
tPLH
tPHL
tPLH
tPHL
tPZH
Tn to En
(Transparent)
LE to En
OE to En
(Cutoff to HIGH)
1.1 3.3 1.1 3.4 1.1 3.6
1.7 3.4 1.7 3.5 1.9 3.7
1.3 4.0 1.5 4.2 1.7 4.6
ns Figures 1, 2
ns Figures 1, 2
ns Figures 1, 2
tPHZ
OE to En
(HIGH to Cutoff)
1.5 4.3 1.6 4.3 1.6 4.4
ns Figures 1, 2
tPHZ
DIR to En
(HIGH to Cutoff)
1.6 4.1 1.6 4.1 1.7 4.3
ns Figures 1, 2
tSET
Tn to LE
1.0 1.0 1.0
tHOLD
Tn to LE
1.0 1.0 1.0
tPW(H)
Pulse Width LE
2.0 2.0 2.0
tTLH Transition Time
0.6 1.6 0.6 1.6 0.6 1.6
tTHL 20% to 80%, 80% to 20%
tOSHL
Maximum Skew Common Edge
Output-to-Output Variation
200 200 200
ns Figures 1, 2
ns Figures 1, 2
ns Figures 1, 2
ns Figures 1, 2
PLCC Only
ps (Note 10)
Data to Output Path
tOSLH
Maximum Skew Common Edge
PLCC Only
Output-to-Output Variation
200 200 200 ps (Note 10)
Data to Output Path
tOST
Maximum Skew Opposite Edge
PLCC Only
Output-to-Output Variation
650 650 650 ps (Note 10)
Data to Output Path
tPS Maximum Skew
PLCC Only
Pin (Signal) Transition Variation
650
650
650 ps (Note 10)
Data to Output Path
Note 10: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same
packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in oppo-
site directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design.
5 www.fairchildsemi.com
5 Page 
Switching Waveforms (ECL-to-TTL) (Continued)
Note: DIR is LOW, LE is HIGH
FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times
Note: OE is HIGH, LE is HIGH
FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 100328QI.PDF ] | |
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