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PDF DAC3550A Data sheet ( Hoja de datos )
| Número de pieza | DAC3550A | |
| Descripción | DAC 3550A STEREO AUDIO DAC | |
| Fabricantes | ETC | |
| Logotipo |  |
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MICRONAS
DAC 3550A
Stereo Audio DAC
Edition July 23, 1999
6251-140697-41EDS
MICRONAS
1 page  
DAC 3550A
2. Functional Description
2.1. I2S Interface
The I2S interface is the digital audio interface between
the DAC 3550A and external digital audio sources
such as CD/DAT players, MPEG decoders etc. It cov-
ers most of the I2S-compatible formats.
All modes have two common features:
1. The MSB is left justified to an I2S frame identifica-
tion (WSI) transition.
2. Data is valid on the rising edge of the bit clock CLI.
16-bit mode
In this case, the bit clock is 32 × fsaudio. Maximum word
length is 16 bit.
32-bit mode
In this case, the bit clock is 64 × fsaudio. Maximum word
length is 32 bit.
Automatic Detection
No I2C control is required to switch between 16- and
32-bit mode. It is recommended to switch the
DAC 3550A into mute position during changing
between 16- and 32-bit mode.
For high-quality audio, it is recommended to use the
32-bit mode of the I2S interface to make use of the full
dynamic range (if more than 16 bits are available).
Left-Right Selection
Standard I2S format defines an audio frame always
starting with left channel and low-state of WSI. How-
ever, I2C control allows changing the polarity of WSI.
Delay Bit
Standard I2S format requires a delay of one clock
cycle between transitions of WSI and data MSB. In
order to fit other formats, however, this characteristic
can be switched off and on by I2C control.
CLI
Vh
Vl
DAI
Vh
Vl
WSI
Vh
Vl
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
programmable delay bit
left 16-bit audio sample
right 16-bit audio sample
Fig. 2–1: I2S 16-bit mode (LR_SEL=0)
CLI
Vh
Vl
DAI
Vh
Vl
WSI
Vh
Vl
31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0
programmable delay bit
left 32-bit audio sample
right 32-bit audio sample
Fig. 2–2: I2S 32-bit mode (LR_SEL=0)
Note: Volume mute should be applied before changing
I2S mode in order to avoid audible clicks.
Micronas
5
5 Page 
DAC 3550A
Pin Pin Name Type
No.
16 SDA
IN/OUT
17 VSS
IN
18 VDD
IN
19 MCS1
IN
20 MCS2
IN
21 DEECTRL IN
22 NC
23 CLI
24 DAI
IN
25 WSI
IN
26 PORQ
IN
27
TESTEN
IN
28 NC
29 AUX2L IN
30 AUX2R IN
31 AUX1L IN
32 AUX1R IN
33 NC
34
DEEML
OUT
35
DEEMR
OUT
36 NC
37 FOUTL OUT
38 FOPL
IN/OUT
39 FINL
IN/OUT
40 NC
41
FOUTR
OUT
42 FOPR
IN/OUT
43 FINR
IN/OUT
44 VREF
IN
Connection
(if not used)
LV
X
X
X
X
VSS
LV
VSS
VSS
VSS
VDD
X
LV
LV
LV
LV
LV
LV
LV
LV
LV
X
X
X
LV
X
X
X
X
Short Description
I2C data
Digital VSS
Digital VDD
I2C Chip Select 1
I2C Chip Select 2
Deemphasis on/off Control
Not connected
I2S Bit Clock
I2S Data
I2S Frame Identification
Power-On Reset, active-low
Test Enable
Not connected
AUX2 left input for external analog signals (e.g. tape)
AUX2 right input for external analog signals (e.g. tape)
AUX1 left input for external analog signals (e.g. FM)
AUX1 right input for external analog signals (e.g. FM)
Not connected
Deemphasis Network Left
Deemphasis Network Right
Not connected
Output to left external filter
Filter op amp inverting input, left
Input for FOUTL or
filter op amp output (line out)
Not connected
Output to right external filter
Right Filter op amp inverting input
Input for FOUTR or
filter op amp output (line out)
Analog reference Ground
Micronas
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DAC3550A.PDF ] | |
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