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PDF DAC1220 Data sheet ( Hoja de datos )
| Número de pieza | DAC1220 | |
| Descripción | 20-Bit Low Power DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DAC1220 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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®
DAC1220
DAC1220
For most current data sheet and other product
information, visit www.burr-brown.com
20-Bit Low Power
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 20-BIT MONOTONICITY GUARANTEED
OVER –40°C to +85°C
q LOW POWER: 2.5mW
q VOLTAGE OUTPUT
q SETTLING TIME: 2ms to 0.012%
q MAX LINEARITY ERROR: ±0.0015%
q ON-CHIP CALIBRATION
DESCRIPTION
The DAC1220 is a 20-bit digital-to-analog (D/A)
converter offering 20-bit monotonic performance over
the specified temperature range. It utilizes delta-sigma
technology to achieve inherently linear performance
in a small package at very-low power. The resolution
of the device can be programmed to 20 bits for full-
scale, settling to 0.003% within 15ms typical, or 16
bits for full-scale, settling to 0.012% within 2ms max.
The output range is two times the external reference
voltage. On-chip calibration circuitry dramatically re-
duces low offset and gain errors.
XIN XOUT VREF
APPLICATIONS
q PROCESS CONTROL
q ATE PIN ELECTRONICS
q CLOSED-LOOP SERVO-CONTROL
q SMART TRANSMITTERS
q PORTABLE INSTRUMENTS
The DAC1220 features a synchronous serial interface.
In single-converter applications, the serial interface
can be accomplished with just two wires, allowing
low-cost isolation. For multiple converters, a CS signal
allows for selection of the appropriate D/A converter.
The DAC1220 has been designed for closed-loop
control applications in the industrial process control
market and high-resolution applications in the test and
measurement market. It is also ideal for remote appli-
cations, battery-powered instruments, and isolated sys-
tems. The DAC1220 is available in a SSOP-16
package.
AVDD AGND
Clock Generator
Microcontroller
Instruction Register
Command Register
Data Register
Offset Register
Full-Scale Register
SDIO
SCLK
Serial
Interface
Second-Order
∆∑
Modulator
First-Order
Switched
Capacitor Filter
Second-Order
Continuous
Time Post Filter
Modulator Control
C1
VOUT
C2
CS
DVDD
DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
PDS-1418B
1
Printed in U.S.A. April , 2000
®
1 page  
THEORY OF OPERATION
The DAC1220 is a precision, high dynamic range, self-
calibrating, 20-bit, delta-sigma digital-to-analog converter.
It contains a second-order delta-sigma modulator, a first-
order switched-capacitor filter, a second-order continuous-
time post filter, a microcontroller including the Instruction,
Command and Calibration registers, a serial interface, and a
clock generator circuit.
The design topology provides low system noise and good
power-supply rejection. The modulator frequency of the
delta-sigma D/A converter is controlled by the system clock.
The DAC1220 also includes complete onboard calibration
that can correct for internal offset and gain errors.
The calibration registers are fully readable and writable.
This feature allows for system calibration. The various
settings, modes, and registers of the DAC1220 are read or
written via a synchronous serial interface. This interface
operates as an externally clocked interface.
DEFINITION OF TERMS
Differential Nonlinearity Error—The differential
nonlinearity error is the difference between an actual step
width and the ideal value of 1 LSB. If the step width is
exactly 1 LSB, the differential nonlinearity error is zero.
A differential nonlinearity specification of less than 1 LSB
guarantees monotonicity.
Drift—The drift is the change in a parameter over tempera-
ture.
Full-Scale Range (FSR)—This is the magnitude of the
typical analog output voltage range which is 2 • VREF.
For example, when the converter is configured with a 2.5V
reference, the full-scale range is 5.0V.
Gain Error—This error represents the difference in the
slope between the actual and ideal transfer functions.
Linearity Error—The linearity error is the deviation of the
actual transfer function from an ideal straight line between
the data end points.
Least Significant Bit (LSB) Weight—This is the ideal
change in voltage that the analog output will change with a
change in the digital input code of 1 LSB.
Monotonicity—Monotonicity assures that the analog out-
put will increase or stay the same for increasing digital input
codes.
Offset Error—The offset error is the difference between
the expected and actual output, when the output is zero. The
value is calculated from measurements made when
VOUT = 20mV.
Settling Time—The settling time is the time it takes the
output to settle to its new value after the digital code has
been changed.
fXIN—The frequency of the crystal oscillator or CMOS-
compatible input signal at the XIN input of the DAC1220.
ANALOG OPERATION
The system clock is divided down to provide the sample
clock for the modulator. The sample clock is used by the
modulator to convert the multi-bit digital input into a one-bit
digital output stream. The use of a 1-bit DAC provides
inherent linearity. The digital output stream is then con-
verted into an analog signal via the 1-bit DAC and then
filtered by the 1st-order switched capacitor filter.
The output of the switched-capacitor filter feeds into the
continuous time filter. The continuous time filter uses exter-
nal capacitors connected between the C1, C2, VREF, and
VOUT pins to adjust the settling time. The connections for the
capacitors are shown in Figure 1 (C1 connects between the
VREF and C1 pins, and C2 connects between the VOUT and C2
pins).
DAC1220
VREF 12
VOUT 11
C2 10
C1 9
C2 C1
FIGURE 1. External Capacitor Connections.
CAPACITOR
16-BIT MODE
C1 2.2nF
C2 0.22nF
TABLE I. External Capacitor Values.
20-BIT MODE
10nF
3.3nF
CALIBRATION
The DAC1220 offers a self-calibration mode which auto-
matically calibrates the output offset and gain. The calibra-
tion is performed once and then normal operation is re-
sumed. In general, calibration is recommended immediately
after power-on and whenever there is a “significant” change
in the operating environment. The amount of change which
should cause a re-calibration is dependent on the applica-
tion. Where high accuracy is important, re-calibration should
be done on changes in temperature and power supply.
After a calibration has been accomplished, the Offset Cali-
bration Register (OCR) and the Full-Scale Calibration Reg-
ister (FCR) contain the results of the calibration.
Note that the values in the calibration registers will vary
from configuration-to-configuration and from part to part.
®
5
5 Page 
Using CS
The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other. The CS
signal does not directly control the tri-state condition of the
SDIO output. These signals are normally in the tri-state
condition. They only become active when serial data is
being transmitted from the DAC1220. If the DAC1220 is in
the middle of a serial transfer and the SDIO is an output,
taking CS HIGH will not tri-state the output signal.
If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, the CS signal must be used. The CS
signal is then used to enable communication with the
DAC1220.
TIMING
The maximum serial clock frequency cannot exceed the
DAC1220 XIN frequency divided by 10. Table IX and
Figures 5 through 9 define the basic digital timing character-
istics of the DAC1220. Figure 5 and the associated timing
symbols apply to the XIN input signal. Figures 6 through 9
and associated timing symbols apply to the serial interface
signals (SCLK, SDIO, and CS). The serial interface is
discussed in detail in the Serial Interface section.
SYMBOL
DESCRIPTION
fXIN XIN Clock Frequency
tXIN XIN Clock Period
t1 XIN Clock High
t2 XIN Clock LOW
t3 SCLK HIGH
t4 SCLK LOW
t5 Data In Valid to SCLK Falling Edge (Setup)
t6 SCLK Falling Edge to Data In Not Valid (Hold)
t7 Data Out Valid After Rising Edge of SCLK (Hold)
t8 SCLK Rising Edge to New Data Out Valid (Delay)(1)
t9 Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data
t10 Falling Edge of CS to Rising Edge of SCLK
t11 Falling Edge of Last SCLK for INSR to SDIO as Output
t12 SDIO as Output to Rising Edge of First SCLK for Register Data
t13 Falling Edge of Last SCLK for Register Data to SDIO Tri-State
t14 Falling Edge of Last SCLK for Register Data to Rising Edge
of First SCLK of next INSR (CS Tied LOW)
t15 Rising Edge of CS to Falling Edge of CS (Using CS)
NOTE: (1) With 10pF load.
TABLE IX. Digital Timing Characteristics.
MIN
1
400
0.4 • tXIN
0.4 • tXIN
5 • tXIN
5 • tXIN
40
20
0
13 • tXIN
11 • tXIN
8 • tXIN
4 • tXIN
41 • tXIN
22 • tXIN
NOM
4 • tXIN
MAX
2.5
1000
50
10 • tXIN
6 • tXIN
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DAC1220.PDF ] | |
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