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PDF DAC1219 Data sheet ( Hoja de datos )

Número de pieza DAC1219
Descripción 12-Bit Binary Multiplying D/A Converter
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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December 1994
DAC1218 DAC1219
12-Bit Binary Multiplying D A Converter
General Description
The DAC1218 and the DAC1219 are 12-bit binary 4-quad-
rant multiplying D to A converters The linearity differential
non-linearity and monotonicity specifications for these con-
verters are all guaranteed over temperature In addition
these parameters are specified with standard zero and full-
scale adjustment procedures as opposed to the impractical
best fit straight line guarantee
This level of precision is achieved though the use of an
advanced silicon-chromium (SiCr) R-2R resistor ladder net-
work This type of thin-film resistor eliminates the parasitic
diode problems associated with diffused resistors and al-
lows the applied reference voltage to range from b25V to
25V independent of the logic supply voltage
CMOS current switches and drive circuitry are used to
achieve low power consumption (20 mW typical) and mini-
mize output leakage current errors (10 nA maximum)
Unique digital input circuitry maintains TTL compatible input
threshold voltages over the full operating supply voltage
range
The DAC1218 and DAC1219 are direct replacements for
the AD7541 series AD7521 series and AD7531 series with
a significant improvement in the linearity specification In
applications where direct interface of the D to A converter to
a microprocessor bus is desirable the DAC1208 and
DAC1230 series eliminate the need for additional interface
logic
Features
Y Linearity specified with zero and full-scale adjust only
Y Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Y Works with g10V reference full 4-quadrant
multiplication
Y All parts guaranteed 12-bit monotonic
Key Specifications
Y Current Settling Time
Y Resolution
Y Linearity (Guaranteed
over temperature)
Y Gain Tempco
Y Low Power Dissipation
Y Single Power Supply
1 ms
12 Bits
12 Bits (DAC1218)
11 Bits (DAC1219)
1 5 ppm C
20 mW
5 VDC to 15 VDC
Typical Application
Connection Diagram
Dual-In-Line Package
 A1 A2 A3
VOUT e bVREF
aaa
248
where AN e 1 if digital input is high
AN e 0 if digital input is low
Ordering Information
JA12
4096
Temperature Range
Non
Linearity
0 012%
0 024%
0 C to a70 C
DAC1218LCJ-1
TL H 5691 – 1
b40 C to a85 C
DAC1218LCJ
DAC1219LCJ
TL H 5691 – 15
Top View
Package Outline
J18A Cerdip
J18A Cerdip
BI-FETTM is a trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL H 5691
RRD-B30M115 Printed in U S A

1 page




DAC1219 pdf
Application Hints
The DAC1218 and DAC1219 are pin-for-pin compatible with
the DAC1220 series but feature 12 and 11-bit linearity spec-
ifications To preserve this degree of accuracy care must
be taken in the selection and adjustments of the output am-
plifier and reference voltage Careful PC board layout is im-
portant with emphasis made on compactness of compo-
nents to prevent inadvertent noise pickup and utilization of
single point grounding and supply distribution
1 0 BASIC CIRCUIT DESCRIPTION
Figure 1 illustrates the R-2R current switching ladder net-
work used in the DAC1218 and DAC1219 As a function of
the logic state of each digital input the binarily weighted
current in each leg of the ladder is switched to either IOUT1
or IOUT2 The voltage potential at IOUT1 and IOUT2 must be
at zero volts to keep the current in each leg the same inde-
pendent of the switch state
The switches operate with a small voltage drop across them
and can therefore conduct currents of either polarity This
permits the reference to be positive or negative thereby
allowing 4-quadrant multiplication by the digital input word
The reference can be a stable DC source or a bipolar AC
signal within the range of g10V for specified accuracy with
an absolute maximum range of g25V The reference can
also exceed the applied VCC of the DAC
The maximum output current from either IOUT1 or IOUT2 is
equal to
 JVREF(max) 4095
R 4096
where R is the reference input resistance (typically 15 kX)
A high level on any digital input steers current to IOUT1 and
a low level steers current to IOUT2
2 0 CREATING A UNIPOLAR OUTPUT VOLTAGE
(A DIGITAL ATTENUATOR)
To generate an output voltage and keep the potential at the
current output terminals at 0V an op amp current to voltage
converter is used As shown in Figure 2 the current from
IOUT1 flows through the feedback resistor forcing a propor-
tional voltage at the amplifier output The voltage at IOUT1 is
held at a virtual ground potential The feedback resistor is
provided on the chip and should always be used as it
matches and tracks the R value of the R-2R ladder The
output voltage is the opposite polarity of the applied refer-
ence voltage
2 1 Amplifier Considerations
To maintain linearity of the output voltage with changing
digital input codes the input offset voltage of the amplifier
must be nulled The resistance from IOUT1 to ground
(RIOUT1) varies non-linearly with the applied digital code
from a minimum of R with all ones applied to the input to
near % with an all zeros code Any offset voltage between
the amplifier inputs appears at the output with a gain of
1 a RF
RIOUT1
Since RIOUT1 varies with the input code any offset will de-
grade output linearity (See Note 4 of Electrical Characteris-
tics )
If the desired amplifier does not have offset balancing pins
available (it could be part of a dual or quad package) the
nulling circuit of Figure 3 can be used The voltage at the
non-inverting input will be set to b VOS initially to force the
inverting input to 0V The common technique of summing
current into the amplifier summing junction cannot be used
as it directly introduces a zero code output current error
Note Switches shown in digital high state
FIGURE 1 The R-2R Current Switching Ladder Network
TL H 5691 – 4
5

5 Page





DAC1219 arduino
Additional Application Ideas (Continued)
DAC Controlled Function Generator
 C1 controls maximum frequency
 k0 5% sine wave THD over range
 Range 30 kHz maximum
 Linearity DAC limit
D
fe
4096 (4 3 RFb C)
Digitally Programmable Pulse-Width Generator
TL H 5691 – 13
lPW j C(7 5V) (4096) (RFb)
D VREF
11
TL H 5691 – 14

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