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PDF DAC0854BIN Data sheet ( Hoja de datos )
| Número de pieza | DAC0854BIN | |
| Descripción | 8-Bit Voltage-Output | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 1995
DAC0854 Quad 8-Bit Voltage-Output
Serial D A Converter with Readback
General Description
The DAC0854 is a complete quad 8-bit voltage-output digi-
tal-to-analog converter that can operate on a single 5V sup-
ply It includes on-chip output amplifiers internal voltage ref-
erence and a serial microprocessor interface By combining
in one package the reference amplifiers and conversion
circuitry for four D A converters the DAC0854 minimizes
wiring and parts count and is hence ideally suited for appli-
cations where cost and board space are of prime concern
The DAC0854 also has a data readback function which can
be used by the microprocessor to verify that the desired
input word has been properly latched into the DAC0854’s
data registers The data readback function simplifies the de-
sign and reduces the cost of systems which need to verify
data integrity
The logic comprises a MICROWIRETM-compatible serial in-
terface and control circuitry The interface allows the user to
write to any one of the input registers or to all four at once
The latching registers are double-buffered consisting of 4
separate input registers and 4 DAC registers Double buffer-
ing allows all 4 DAC outputs to be updated simultaneously
The four reference inputs allow the user to configure the
system to have a separate output voltage range for each
DAC The output voltage of each DAC can range between
0 3V and 2 8V and is a function of VBIAS VREF and the
input word
Features
Y Single a5V supply operation
Y MICROWIRE serial interface allows easy interface to
many popular microcontrollers including the COPSTM
and HPCTM families of microcontrollers
Y Data readback capability
Y Output data can be formatted to read back MSB or
LSB first
Y Versatile logic allows selective or global update of the
DACs
Y Power fail flag
Y Output amplifiers can drive 2 kX load
Y Synchronous asynchronous update of the DAC outputs
Key Specifications
Y Guaranteed monotonic over temperature
Y Integral linearity error
g LSB max
Y Output settling time
2 7 ms max
Y Analog output voltage range
0 3V to 2 8V
Y Supply voltage range
4 5V to 5 5V
Y Clock frequency
10 MHz max
Y Power dissipation (fCLK e 10 MHz)
95 mW max
Y On-board reference
2 65V g2% max
Applications
Y Automatic test equipment
Y Industrial process controls
Y Automotive controls and diagnostics
Y Instrumentation
Connection Diagram
Ordering Information
Industrial (b40 C k TA a85 C)
Package
DAC0854BIN DAC0854CIN
N20A Molded DIP
DAC0854CIJ
J20A Ceramic DIP
DAC0854BIWM DAC0854CIWM M20B Small Outline
Military (b55 C k TA k a125 C)
DAC0854CMJ 883
J20A Ceramic DIP
Top View
TL H 11261 – 1
COPSTM HPCTM and MICROWIRETM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11261
RRD-B30M75 Printed in U S A
1 page  
Typical Converter Performance Characteristics
Zero Error vs
Temperature
Full-Scale Error
vs Temperature
Supply Current
vs Temperature
Zero Error PSRR
vs Temperature
Full-Scale Error PSRR
vs Temperature
Supply Current vs
Clock Frequency
Typical Reference Performance Characteristics
Bandgap Voltage
vs Temperature
Line Regulation
vs Temperature
TL H 11261 – 2
TL H 11261 – 3
5
TL H 11261 – 4
5 Page 
Digital Interface (Continued)
Table III lists the instruction set for the READ mode By the
appropriate setting of the global (G) and address (A1 and
A0) bits one can select a specific DAC to be read or one
can read all the DACs in succession starting with DAC 1
The R F bit determines whether the data changes on the
rising or the falling edge of the system clock With the R F
bit high the data changes on the rising edge that occurs 1
clock cycles after the end of the instruction byte With the
R F bit low the data changes on the falling edge that oc-
curs 1 clock cycle after the end of the instruction byte One
can choose to read the data back MSB first or LSB first by
setting the M L bit (See Figures 3 and 4 )
An asynchronous update of all the DAC outputs can be
achieved by taking AU low The contents of the input regis-
ters are loaded into the DAC registers with the update oc-
curring on the falling edge of AU CS must be held high
during an asynchronous update
All DAC registers will have their contents reset to all zeros
on power up
TABLE III READ MODE Instruction Set
SB
Bit 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RD WR
Bit 2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
G
Bit 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
RF
Bit 4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
ML
Bit 5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
A1
Bit 6
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
A0
Bit 7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
Description
Read DAC 1 LSB first data changes on the falling edge
Read DAC 2 LSB first data changes on the falling edge
Read DAC 3 LSB first data changes on the falling edge
Read DAC 4 LSB first data changes on the falling edge
Read DAC 1 MSB first data changes on the falling edge
Read DAC 2 MSB first data changes on the falling edge
Read DAC 3 MSB first data changes on the falling edge
Read DAC 4 MSB first data changes on the falling edge
Read DAC 1 LSB first data changes on the rising edge
Read DAC 2 LSB first data changes on the rising edge
Read DAC 3 LSB first data changes on the rising edge
Read DAC 4 LSB first data changes on the rising edge
Read DAC 1 MSB first data changes on the rising edge
Read DAC 2 MSB first data changes on the rising edge
Read DAC 3 MSB first data changes on the rising edge
Read DAC 4 MSB first data changes on the rising edge
Read all DACs LSB first data changes on the falling edge
Read all DACs MSB first data changes on the falling edge
Read all DACs LSB first data changes on the rising edge
Read all DACs MSB first data changes on the rising edge
Power Fail Function
If a power failure occurs on the system using the DAC0854
then the INT pin will be pulled low on the next power-up
cycle To force this output high again and reset this flag the
CS pin will have to be brought low When this is done the
INT output will be pulled high again via an external 10 kX
pull-up resistor This feature may be used by the microproc-
essor to discard data whose integrity is in question
Power Supplies
The DAC0854 is designed to operate from a a5V (nominal)
supply There are two supply pins AVCC and DVCC These
pins allow separate external bypass capacitors for the ana-
log and digital portions of the circuit To guarantee accurate
conversions the two supply pins should each be bypassed
with a 0 1 mF ceramic capacitor in parallel with a 10 mF
tantalum capacitor
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DAC0854BIN.PDF ] | |
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