DataSheet.es    


PDF DAC0832 Data sheet ( Hoja de datos )

Número de pieza DAC0832
Descripción 8-Bit P Compatible/ Double-Buffered D to A Converters
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de DAC0832 (archivo pdf) en la parte inferior de esta página.


Total 24 Páginas

No Preview Available ! DAC0832 Hoja de datos, Descripción, Manual

May 1999
DAC0830/DAC0832
8-Bit µP Compatible, Double-Buffered D to A Converters
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent tem-
perature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors.
Special circuitry provides TTL logic input voltage level com-
patibility.
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number
of DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DAC).
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only — NOT BEST STRAIGHT LINE FIT.
n Works with ±10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates “STAND ALONE” (without µP) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Key Specifications
n Current settling time: 1 µs
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/˚C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 VDC
Typical Application
BI-FETand MICRO-DACare trademarks of National Semiconductor Corporation.
Z80® is a registered trademark of Zilog Corporation.
© 1999 National Semiconductor Corporation DS005608
DS005608-1
www.national.com

1 page




DAC0832 pdf
Electrical Characteristics (Continued)
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJMAX = 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N pack-
age, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
by approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01% linearity error.
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at VREF=±10 VDC and VREF=±1 VDC.
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-
ticular VREF value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees that
after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xVREF of a straight
line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
Note 10: A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (100x10−9x20x103)x100/10 which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply.
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 kresistor.
Switching Waveform
DS005608-2
5 www.national.com

5 Page





DAC0832 arduino
DAC0830 Series Application Hints (Continued)
DS005608-8
FIGURE 5. Accommodating a High Speed System
2.0 ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to pro-
vide an accurate analog output quantity which is representa-
tive of the applied digital word. In the case of the DAC0830,
the output, IOUT1, is a current directly proportional to the
product of the applied reference voltage and the digital input
word. For application versatility, a second output, IOUT2, is
provided as a current directly proportional to the complement
of the digital input. Basically:
where the digital input is the decimal (base 10) equivalent of
the applied 8-bit binary word (0 to 255), VREF is the voltage
at pin 8 and 15 kis the nominal value of the internal resis-
tance, R, of the R-2R ladder network (discussed in Section
2.1).
Several factors external to the DAC itself must be consid-
ered to maintain analog accuracy and are covered in subse-
quent sections.
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromium
(SiCr or Si-chrome) thin film R-2R ladder which is deposited
on the surface oxide of the monolithic chip. As a result, there
are no parasitic diode problems with the ladder (as there
may be with diffused resistors) so the reference voltage,
VREF, can range −10V to +10V even if VCC for the device is
5VDC.
The digital input code to the DAC simply controls the position
of the SPDT current switches and steers the available ladder
current to either IOUT1 or IOUT2 as determined by the logic in-
put level (“1” or “0”) respectively, as shown in Figure 6. The
MOS switches operate in the current mode with a small volt-
age drop across them and can therefore switch currents of
either polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the ap-
plied digital code, it is important that the voltages at both of
the current output pins be as near ground potential (0VDC)
as possible. With VREF=+10V every millivolt appearing at ei-
ther IOUT1 or IOUT2 will cause a 0.01% linearity error. In most
applications this output current is converted to a voltage by
using an op amp as shown in Figure 7.
The inverting input of the op amp is a “virtual ground” created
by the feedback from its output through the internal 15 kre-
sistor, Rfb. All of the output current (determined by the digital
input and the reference voltage) will flow through Rfb to the
output of the amplifier. Two-quadrant operation can be ob-
tained by reversing the polarity of VREF thus causing IOUT1 to
flow into the DAC and be sourced from the output of the am-
plifier. The output voltage, in either case, is always equal to
IOUT1xRfb and is the opposite polarity of the reference volt-
age.
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from −10V to +10V. The
DAC can be thought of as a digitally controlled attenuator:
the output voltage is always less than or equal to the applied
reference voltage. The VREF terminal of the device presents
a nominal impedance of 15 kto ground to external circuitry.
Always use the internal Rfb resistor to create an output volt-
age since this resistor matches (and tracks with tempera-
ture) the value of the resistors used to generate the output
current (IOUT1).
11 www.national.com

11 Page







PáginasTotal 24 Páginas
PDF Descargar[ Datasheet DAC0832.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
DAC0830Double-Buffered D to A ConvertersNational Semiconductor
National Semiconductor
DAC0830DAC0830/DAC0832 8-Bit uP Compatible Double-Buffered D to A Converters (Rev. B)Texas Instruments
Texas Instruments
DAC0830LCJ8-Bit P Compatible/ Double-Buffered D to A ConvertersNational Semiconductor
National Semiconductor
DAC0830LCM8-Bit P Compatible/ Double-Buffered D to A ConvertersNational Semiconductor
National Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar