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PDF DDC101 Data sheet ( Hoja de datos )
| Número de pieza | DDC101 | |
| Descripción | 20-BIT ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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®
DDC101
DDC101
20-BIT ANALOG-TO-DIGITAL CONVERTER
FEATURES
q MONOLITHIC CHARGE INPUT ADC
q DIGITAL FILTER NOISE REDUCTION:
0.9ppm, rms
q DIGITAL ERROR CORRECTION: CDS
q CONVERSION RATE: Up to 15kHz
q USER FRIENDLY EVALUATION FIXTURE
APPLICATIONS
q DIRECT PHOTOSENSOR DIGITIZATION
q PRECISION INSTRUMENTATION
q INFRARED PYROMETRY
q PRECISION PROCESS CONTROL
q CT SCANNER DAS
q CHEMICAL ANALYZERS
DESCRIPTION
The DDC101 is a precision, wide dynamic range, charge
digitizing A/D converter with 20-bit resolution. Low
level current output devices, such as photosensors, can be
directly connected to its input. The most stringent accu-
racy requirements of many unipolar output sensor appli-
cations occur at low signal levels. To meet this require-
ment, Burr-Brown developed the adaptive delta modula-
tion architecture of the DDC101 to provide linearly
improving noise and linearity errors as the input signal
level decreases. The DDC101 combines the functions of
current-to-voltage conversion, integration, input program-
mable gain amplification, A/D conversion, and digital
filtering to produce precision, wide dynamic range re-
sults. The input signal can be a low level current con-
nected directly into the unit or a voltage connected
through a user selected resistor. Although the DDC101 is
optimized for unipolar signals, it can also accurately
digitize bipolar input signals. The patented delta modula-
tion topology combines charge integration and digitiza-
tion functions. Oversampling and digital filtering reduce
system noise dramatically. Correlated Double Sampling
(CDS) captures and eliminates steady state and conver-
sion cycle dependent offset and switching errors that are
not eliminated with conventional analog circuits.
The DDC101 block diagram is shown below. During
conversion, the input signal is collected on the internal
integration capacitance for a user determined integration
period. A high precision, autozeroed comparator samples
the analog input node. Tracking logic updates the internal
high resolution D/A converter at a 2MHz rate to maintain
the analog input at virtual ground. A user programmable
digital filter oversamples the tracking logic’s output. The
digital filter passes a low noise, high resolution digital
output to the serial I/O register. The serial outputs of
multiple DDC101 units can be easily connected together
in series or parallel if desired to minimize interconnections.
Test In
+VS
Test Current
Reset
DDC101 Integrated Circuit
CDAC
CINT
DAC
18 Bits
Analog
Input
Ground
Comparator
Digital Integration,
Tracking and
Control Logic
20 Bits
Digital Filter and
Error Correction
Oversampled
Digital Out
Serial I/O
Register
Serial In
Serial Out
VREF Setup
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1993 Burr-Brown Corporation
PDS-1211E
Printed in U.S.A. March, 1998
1 page  
SPECIFICATIONS (CONT)
ELECTRICAL
All specifications with unipolar current input range, TINT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC,
unless otherwise noted.
PARAMETER
CONDITIONS
DDC101
MIN
TYP
MAX
UNITS
POWER SUPPLY REQUIREMENTS
Operation(5)
Quiescent Current, Positive Supply
Analog, VS+
Digital, VDD+
Quiescent Current, Negative Supply
Operating Power
VS+ = +5VDC, VDD+ = +5VDC
V – = –5VDC
S
±4.75
±5
15.6
8.9
6.7
18.0
170
±5.25
19.5
22.5
VDC
mA
mA
mA
mA
mW
TEMPERATURE RANGE
Operating
Storage
–40 +85 °C
–60
+100
°C
NOTES: (1) Input = low level (less than 1% of Full Scale); Full Scale IIN = 500nA; TINT = 1ms; Unipolar Input Range; Acquisition Time = 16 clock cycles, Oversampling = 128. (2) Voltage input is converted through user
provided input resistor, R . (3) FSR is Full Scale Range. (4) Gain Drift does not include the drift of the external reference. (5) V + must be less than or equal to V +. See Section 7 for recommended connections. (6)
IN DD S
Straight Binary output code has slightly different Charge Range. See Section 6. (8) Input offset voltage is nulled by autozero circuitry and causes no output error. See Section 6 (Internal Error Correction). (9) This is
the maximum clock frequency at which SETUP codes can be written to and read from the DDC101. (10) For other input current and voltage configurations, see Discussion of Specifications and Detailed Theory of Operation
sections. (11) A best-fit straight line method is used to determine linearity. Two different best-fit straight lines are used for the two unipolar integral linearity specifications. Acquisition Time = 16 clock cycles, Oversampling
= 128.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
THERMAL
RESISTANCE (θJA)
(°C/W)
DDC101U
24-Lead SOIC
239
100
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
Analog Inputs
Input Current ............................................................ 100mA, momentary
Input Current .............................................................. 10mA, continuous
Input Voltage ................................................... VS+ +0.5V to VS– –0.5V
Power Supply
VS+ .................................................................................................. + 7V
VS– .................................................................................................... –7V
VDD+ ................................................................................. must be ≤ VS+
Maximum Junction Temperature ................................................... +165°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
5 DDC101
5 Page 
TYPICAL PERFORMANCE CURVES (CONT)
ELECTRICAL
System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted.
NOISE vs INPUT CAPACITANCE, UNIPOLAR INPUT
40
1ms Integration Time
35 M = 128 Oversamples
30
25
No CDS
20
15
10
5
CDS On, K = 16
0
0
100
200
500
1000
2000
CIN (pF)
NOISE vs OVERSAMPLING, UNIPOLAR INPUT
50
1ms Integration Time
K = 16 Acquisition Clocks
CIN = 0pF
10
L = 1 Integration/Conversion
1.0
L = 128 L = 64
L = 256
L = 32
L = 16
L=2
L=8 L=4
0.5
1 2 4 8 16 32 64 128 256
M Oversamples
CHANGE IN IB vs TEMPERATURE
2.0
0
–2.0
–4.0
–6.0
–8.0
–40
–20
0 20 40 60
Temperature (°C)
80 100
NOISE vs TEMPERATURE, UNIPOLAR INPUT
5
1ms Integration Time
K = 16 Acquisition Clocks
4 M = 128 Oversamples
3
2
1
0
–40
–20
0
25 45 65 85
Temperature (°C)
NOISE vs INTEGRATION TIME, UNIPOLAR INPUT
5 K = 16 Acquisition Clocks
CIN = 0pF
M = 16 O/S
4
3
2 M = 64 O/S
M = 256 O/S
1
0
0.1
1 10
Integration Time (ms)
100
0.050
INPUT OFFSET VOLTAGE vs INPUT CAPACITANCE
0.000
–0.050
0.100
–0.150
–0.200
–0.250
–0.300
0
100
CIN (pF)
500
®
11 DDC101
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet DDC101.PDF ] | |
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