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PDF DAC902E Data sheet ( Hoja de datos )

Número de pieza DAC902E
Descripción 12-Bit/ 165MSPS DIGITAL-TO-ANALOG CONVERTER
Fabricantes Burr-Brown Corporation 
Logotipo Burr-Brown Corporation Logotipo



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No Preview Available ! DAC902E Hoja de datos, Descripción, Manual

®
DAC902
DAC902
For most current data sheet and other product
information, visit www.burr-brown.com
DAC902
TM 12-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q SINGLE +5V OR +3V OPERATION
q HIGH SFDR: 5MHz Output at 100MSPS: 67dBc
q LOW GLITCH: 3pV-s
q LOW POWER: 170mW at +5V
q INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
APPLICATIONS
q COMMUNICATION TRANSMIT CHANNELS:
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
q WAVEFORM GENERATION:
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
q MEDICAL/ULTRASOUND
q HIGH-SPEED INSTRUMENTATION AND
CONTROL
q VIDEO, DIGITAL TV
DESCRIPTION
The DAC902 is a high-speed, digital-to-analog converter (DAC)
offering a 12-bit resolution option within the SpeedPlus Family
of high-performance converters. Featuring pin compatibility
among family members, the DAC908, DAC900, and DAC904
provide a component selection option to an 8-, 10-, and 14-bit
resolution, respectively. All models within this family of D/A
converters support update rates in excess of 165MSPS with
excellent dynamic performance, and are especially suited to
fulfill the demands of a variety of applications.
The advanced segmentation architecture of the DAC902 is
optimized to provide a high Spurious-Free Dynamic Range
(SFDR) for single-tone, as well as for multi-tone signals—
essential when used for the transmit signal path of communica-
tion systems.
The DAC902 has a high impedance (200k) current output with
a nominal range of 20mA and an output compliance of up to
1.25V. The differential outputs allow for both a differential, or
single-ended analog signal interface. The close matching of the
current outputs ensures superior dynamic performance in the
differential configuration, which can be implemented with a
transformer.
Utilizing a small geometry CMOS process, the monolithic
DAC902 can be operated on a wide, single-supply range of
+2.7V to +5.5V. Its low power consumption allows for use in
portable and battery operated systems. Further optimization can
be realized by lowering the output current with the adjustable
full-scale option.
For noncontinuous operation of the DAC902, a power-down
mode results in only 45mW of standby power.
The DAC902 comes with an integrated 1.24V bandgap refer-
ence and edge-triggered input latches, offering a complete
converter solution. Both +3V and +5V CMOS logic families
can be interfaced to the DAC902.
The reference structure of the DAC902 allows for additional
flexibility by utilizing the on-chip reference, or applying an
external reference. The full-scale output current can be adjusted
over a span of 2mA to 20mA, with one external resistor, while
maintaining the specified dynamic performance.
The DAC902 is available in the SO-28 and TSSOP-28 pack-
ages.
+VA
DAC902
FSA
REFIN
INT/EXT
BW +VD
Current
Sources
LSB
Switches
Segmented
Switches
IOUT
IOUT
BYP
+1.24V Ref.
AGND
CLK
Latches
PD
12-Bit Data Input
D11...D0
DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1999 Burr-Brown Corporation
PDS-1447B
Printed in U.S.A. May, 2000

1 page




DAC902E pdf
TIMING DIAGRAM
CLK
D11 - D0
t1
tS tH
t2
IOUT
or
IOUT
tPD
tSET
SYMBOL
t1
t2
tS
tH
tPD
tSET
DESCRIPTION
Clock Pulse High Time
Clock Pulse Low Time
Data Setup Time
Data Hold Time
Propagation Delay Time
Output Settling Time to 0.1%
MIN
TYP
MAX
3.0
3.0
1.5
2.5
(t1 + t2) + 1
30.0
UNITS
ns
ns
ns
ns
ns
ns
®
5 DAC902

5 Page





DAC902E arduino
APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC902 uses the current steering
technique to enable fast switching and a high update rate.
The core element within the monolithic D/A converter is an
array of segmented current sources, which are designed to
deliver a full-scale output current of up to 20mA (see
Figure 1). An internal decoder addresses the differential
current switches each time the DAC is updated and a
corresponding output current is formed by steering all
currents to either output summing node, IOUT or IOUT.
The complementary outputs deliver a differential output
signal, which improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by
a factor of two, compared to single-ended operation.
The segmented architecture results in a significant reduc-
tion of the glitch energy, improves the dynamic perfor-
mance (SFDR), and DNL. The current outputs maintain a
very high output impedance of greater than 200k.
The full-scale output current is determined by the ratio of
the internal reference voltage (1.24V) and an external
resistor, RSET. The resulting IREF is internally multiplied by
a factor of 32 to produce an effective DAC output current
that can range from 2mA to 20mA, depending on the value
of RSET.
The DAC902 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the cur-
rent source array with its associated switches, and the
reference circuitry.
DAC TRANSFER FUNCTION
The total output current, IOUTFS, of the DAC902 is the
summation of the two complementary output currents:
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/4096)
(2)
IOUT = IOUTFS • (4095 - Code/4096)
(3)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the refer-
ence current IREF, which is determined by the reference
voltage and the external setting resistor, RSET.
IOUTFS = 32 • IREF = 32 • VREF /RSET
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
VOUT = IOUT • RLOAD
VOUT = IOUT • RLOAD
(5)
(6)
Full-Scale
Adjust
Resistor
RSET
2k
+3V to +5V
Analog
0.1µF
+3V to +5V
Digital
DAC902 +VA
FSA
Ref
Input REFIN
Ref
Control
Amp
0.1µF
INT/EXT Ref
Buffer
+1.24V Ref
AGND
Bandwidth
Control
BW +VD
400pF
PMOS
Current
Source
Array
LSB
Switches
IOUT
IOUT
Segmented
MSB
Switches
BYP
0.1µF
50
20pF
Latches and Switch
Decoder Logic
PD
Power Down
(internal pull-down)
CLK
12-Bit Data Input DGND
Analog
Ground
Clock
Input
D11...D0
Digital
Ground
50
1:1
VOUT
20pF
NOTE: Supply bypassing not shown.
FIGURE 1. Functional Block Diagram of the DAC902.
11
DAC902
®

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