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PDF DAC8532 Data sheet ( Hoja de datos )

Número de pieza DAC8532
Descripción Dual Channel/ Low Power/ 16-Bit/ Serial Input DIGITAL-TO-ANALOG CONVERTER
Fabricantes Burr-Brown Corporation 
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DAC8532
SBAS246A – DECEMBER 2001 – MAY 2003
Dual Channel, Low Power, 16-Bit, Serial Input
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q microPOWER OPERATION: 500µA at 5V
q POWER-ON RESET TO ZERO-SCALE
q POWER SUPPLY: +2.7V to +5.5V
q 16-BIT MONOTONIC OVER TEMPERATURE
q SETTLING TIME: 10µs to ±0.003% FSR
q ULTRA-LOW AC CROSSTALK: –100dB typ
q LOW-POWER SERIAL INTERFACE WITH
SCHMITT-TRIGGERED INPUTS
q ON-CHIP OUTPUT BUFFER AMPLIFIER WITH
RAIL-TO-RAIL OPERATION
q DOUBLE BUFFERED INPUT ARCHITECTURE
q SIMULTANEOUS OR SEQUENTIAL OUTPUT
UPDATE AND POWERDOWN
q TINY MSOP-8 PACKAGE
APPLICATIONS
q PORTABLE INSTRUMENTATION
q CLOSED-LOOP SERVO-CONTROL
q PROCESS CONTROL
q DATA ACQUISITION SYSTEMS
q PROGRAMMABLE ATTENUATION
q PC PERIPHERALS
VDD
DESCRIPTION
The DAC8532 is a dual channel, 16-bit Digital-to-Analog
Converter (DAC) offering low power operation and a flexible
serial host interface. Each on-chip precision output amplifier
allows rail-to-rail output swing to be achieved over the supply
range of 2.7V to 5.5V. The device supports a standard 3-wire
serial interface capable of operating with input data clock
frequencies up to 30MHz for VDD = 5V.
The DAC8532 requires an external reference voltage to set
the output range of each DAC channel. Also incorporated
into the device is a power-on reset circuit which ensures that
the DAC outputs power up at zero-scale and remain there
until a valid write takes place. The DAC8532 provides a
flexible power-down feature, accessed over the serial inter-
face, that reduces the current consumption of the device to
200nA at 5V.
The low-power consumption of this device in normal opera-
tion makes it ideally suited to portable battery-operated
equipment and other low-power applications. The power
consumption is 2.5mW at 5V, reducing to 1µW in power-
down mode.
The DAC8532 is available in a MSOP-8 package with a
specified operating temperature range of –40°C to +105°C.
VREF
Data
Buffer A
DAC
Register A
DAC A
VOUTA
SYNC
SCLK
DIN
Data
Buffer B
DAC
Register B
DAC B
16
24-Bit
Serial-to-
Channel
Load
Parallel
Select
Control
Shift 8
Register
Control Logic
2
GND
Power-Down
Control Logic
Resistor
Network
VOUTB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2001-2003, Texas Instruments Incorporated

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DAC8532 pdf
TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
64
48
32
16
VDD = VREF = 5V, TA = 25°C,
Channel A Output
0
16
32
48
64
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
0000H 2000H
4000H
6000H
8000H
A000H C000H
E000H FFFFH
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
64
48 VDD = VREF = 2.7V, TA = 25°C,
32 Channel A Output
16
0
16
32
48
64
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
0000H
2000H
4000H 6000H
8000H
A000H C000H
E000H FFFFH
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
64
48
32
16
0
16
32
48
VDD = VREF = 5V, TA = 25°C,
Channel B Output
64
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
0000H
2000H
4000H 6000H
8000H
A000H C000H
E000H FFFFH
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
64
48
32
16
0
16
32
48
VDD = VREF = 2.7V, TA = 25°C,
Channel B Output
64
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
0000H
2000H
4000H 6000H
8000H
A000H C000H
E000H FFFFH
Digital Input Code
ZERO-SCALE ERROR vs TEMPERATURE
25
VDD = VREF
VDD = 5V, CH B
20
VDD = 5V, CH A
15
10
5
0
40
VDD = 2.7V, CH B
VDD = 2.7V, CH A
10 20
50 80 105
Temperature (°C)
FULL-SCALE ERROR vs TEMPERATURE
15
(To avoid clipping of the output signal
10 during the test, VREF = VDD 10mV)
5
VDD = 2.7V, CH B
0
VDD = 5V, CH B
5
10
15
40
VDD = 2.7V, CH A
VDD = 5V, CH A
10 20
50
Temperature (°C)
80
105
DAC8532
SBAS246A
www.ti.com
5

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DAC8532 arduino
INPUT SHIFT REGISTER
The input shift register of the DAC8532 is 24 bits wide (see
Figure 5) and is made up of 8 control bits (DB16-DB23) and 16
data bits (DB0-DB15). The first two control bits (DB22 and
DB23) are reserved and must be 0for proper operation. LD
A (DB20) and LD B (DB21) control the updating of each analog
output with the specified 16-bit data value or power-down
command. Bit DB19 is a Don't Carebit which does not affect
the operation of the DAC8532 and can be 1 or 0. The following
control bit, Buffer Select (DB18), controls the destination of the
data (or power-down command) between DAC A and DAC B.
The final two control bits, PD0 (DB16) and PD1 (DB17), select
the power-down mode of one or both of the DAC channels. The
four modes are normal mode or any one of three power-down
modes. A more complete description of the operational modes
of the DAC8532 can be found in the Power-Down Modes
section. The remaining sixteen bits of the 24-bit input word
make up the data bits. These are transferred to the specified
Data Buffer or DAC Register, depending on the command
issued by the control byte, on the 24th falling edge of SCLK.
Please refer to Tables II and III for more information.
Resistor
String DAC
Amplifier
VOUTX
Power-down
Circuitry
Resistor
Network
FIGURE 3. Output Stage During Power-Down (High-Impedance)
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept LOW for
at least 24 falling edges of SCLK and the addressed DAC
register is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it acts as
an interrupt to the write sequence; the shift register is reset
and the write sequence is discarded. Neither an update of
the data buffer contents, DAC register contents or a change
in the operating mode occurs (see Figure 4).
POWER-ON RESET
The DAC8532 contains a power-on reset circuit that con-
trols the output voltage during power-up. On power-up, the
DAC registers are filled with zeros and the output voltages
are set to zero-scale; they remain there until a valid write
sequence and load command is made to the respective
DAC channel. This is useful in applications where it is
important to know the state of the output of each DAC
output while the device is in the process of powering up.
No device pin should be brought high before power is
applied to the device.
POWER-DOWN MODES
The DAC8532 utilizes four modes of operation. These modes
are accessed by setting two bits (PD1 and PD0) in the control
register and performing a Loadaction to one or both DACs.
Table I shows how the state of the bits correspond to the
mode of operation of each channel of the device. (Each DAC
channel can be powered down simultaneously or indepen-
dently of each other. Power-down occurs after proper data is
written into PD0 and PD1 and a Loadcommand occurs.)
Please refer to the "Operation Examples" section for addi-
tional information.
PD1 (DB17)
0
0
1
1
PD0 (DB16)
0
1
0
1
OPERATING MODE
Normal Operation
Power-Down Modes
Output Typically 1kto GND
Output Typically 100kto GND
High Impedance
TABLE I. Modes of Operation for the DAC8532.
When both bits are set to 0, the device works normally with
a typical power consumption of 500µA at 5V. For the three
power-down modes, however, the supply current falls to
200nA at 5V (50nA at 3V). Not only does the supply current
fall but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the
device is known while it is in power-down mode. There are
three different options for power-down: The output is con-
nected internally to GND through a 1kresistor, a 100k
resistor, or it is left open-circuited (High-Impedance). The
output stage is illustrated in Figure 3.
All analog circuitry is shut down when the power-down mode
is activated. Each DAC will exit power-down when PD0 and
PD1 are set to 0, new data is written to the Data Buffer, and
the DAC channel receives a Loadcommand. The time to
exit power-down is typically 2.5µs for VDD = 5V and 5µs for
VDD = 3V (See the Typical Characteristics).
DAC8532
SBAS246A
www.ti.com
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