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PDF DAC8512EP Data sheet ( Hoja de datos )
| Número de pieza | DAC8512EP | |
| Descripción | % V/ Serial Input Complete 12-Bit DAC | |
| Fabricantes | Analog Devices | |
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FEATURES
Space Saving SO-8 or Mini-DIP Packages
Complete, Voltage Output with Internal Reference
1 mV/Bit with 4.095 V Full Scale
Single +5 Volt Operation
No External Components
3-Wire Serial Data Interface, 20 MHz Data Loading Rate
Low Power: 2.5 mW
APPLICATIONS
Portable Instrumentation
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
PC Peripherals
+5 V, Serial Input
Complete 12-Bit DAC
DAC8512
FUNCTIONAL BLOCK DIAGRAM
CLR 6
LD 5
CS 2
CLK 3
SDI 4
REF
12-BIT DAC
12
DAC REGISTER
12
SERIAL REGISTER
1 VDD
8 VOUT
7 GND
GENERAL DESCRIPTION
The DAC8512 is a complete serial input, 12-bit, voltage output
digital-to-analog converter designed to operate from a single
+5 V supply. It contains the DAC, input shift register and
latches, reference and a rail-to-rail output amplifier. Built using
a CBCMOS process, these monolithic DACs offer the user low
cost, and ease of use in +5 V only systems.
Coding for the DAC8512 is natural binary with the MSB loaded
first. The output op amp can swing to either rail and is set to a
range of 0 V to +4.095 V—for a one-millivolt-per-bit resolution.
It is capable of sinking and sourcing 5 mA. An on-chip reference
is laser trimmed to provide an accurate full-scale output voltage
of 4.095 V.
Serial interface is high speed, three-wire, DSP compatible with
data in (SDI), clock (CLK) and load strobe (LD). There is also
a chip-select pin for connecting multiple DACs.
A CLR input sets the output to zero scale at power on or upon
user demand.
The DAC8512 is specified over the extended industrial (–40°C
to +85°C) temperature range. DAC8512s are available in plas-
tic DIPs and SO-8 surface mount packages.
1.0
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1.0
0
1024
2048
3072
DIGITAL INPUT CODE – Decimal
Linearity Error vs. Digital Input Code
4096
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
1 page  
DAC8512
PIN CONFIGURATIONS
SO-8
P-DIP-8 & Cerdip-8
VDD 1
8 VOUT
CS 2 DAC8512 7 GND
CLK 3 TOP VIEW 6 CLR
(Not to Scale)
SDI 4
5 LD
VDD 1
CS 2
CLK 3
SDI 4
DAC8512
TOP VIEW
(Not to Scale)
8 VOUT
7 GND
6 CLR
5 LD
PIN DESCRIPTIONS
Pin Name Description
1 VDD Positive Supply. Nominal value +5 V, ± 5%.
2 CS Chip Select. Active low input.
3 CLK Clock input for the internal serial input shift register.
4 SDI Serial Data Input. Data on this pin is clocked into the
internal serial register on positive clock edges of the
CLK pin. The Most Significant Bit (MSB) is loaded
first.
5 LD Active low input which writes the serial register data
into the DAC register. Asynchronous input.
6 CLR Active low digital input that clears the DAC register to
zero, setting the DAC to minimum scale. Asynchronous
input.
7 GND Analog ground for the DAC. This also serves as the
digital logic ground reference voltage.
8 VOUT Voltage output from the DAC. Fixed output voltage
range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed
full-scale voltage independent of time, temperature and
power supply variations.
DICE CHARACTERISTICS
VDD
1
VOUT
8
7 GND
7 GND
6 CLR
CS 2
CLK 3
45
SDI LD
SUBSTRATE IS COMMON WITH VDD.
NUMBER OF TRANSISTORS : 642
DIE SIZE: 0.055 inch × 0.106 inch; 5830 sq mils
OPERATION
The DAC8512 is a complete ready to use 12-bit digital-to-analog
converter. It contains a voltage-switched, 12-bit, laser-trimmed
DAC, a curvature-corrected bandgap reference, a rail-to-rail
output op amp, a DAC register, and a serial data input register.
The serial data interface consists of a CLK, serial data in (SDI),
and a load strobe (LD). This basic 3-wire interface offers maxi-
mum flexibility for interface to the widest variety of serial data
input loading requirements. In addition a CS select is provided
for multiple packaging loading and a power on reset CLR pin to
simplify start or periodic resets.
D/A CONVERTER SECTION
The DAC is a 12-bit voltage mode device with an output that
swings from GND potential to the 2.5 volt internal bandgap
voltage. It uses a laser trimmed R-2R ladder which is switched
by N channel MOSFETs. The output voltage of the DAC has a
constant resistance independent of digital input code. The DAC
output is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
The DAC’s output is buffered by a low power consumption pre-
cision amplifier. This amplifier contains a differential PNP pair
input stage which provides low offset voltage and low noise, as
well as the ability to amplify the zero-scale DAC output volt-
ages. The rail-to-rail amplifier is configured in a gain of 1.6384
(= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output
(1 mV/LSB). See Figure 3 for an equivalent circuit schematic of
the analog section.
BANDGAP
REFERENCE
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
2R
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
BUFFER
2.5V
R
2R
R
2R
R2
R1
VOUT
AV = 4.095/2.5
= 1.638V/V
SPDT
N-CH FET
SWITCHES
2R
2R
Figure 3. Equivalent DAC8512 Schematic of Analog
Portion
The op amp has a 16 µs typical settling time to 0.01%. There
are slight differences in settling time for negative slowing signals
vs. positive. See the oscilloscope photos in the typical perfor-
mances section of this data sheet.
REV. A
–5–
5 Page 
DAC8512
Table III. Bipolar Code Table
Hexadecimal Number Decimal Number Analog Output
in DAC Register
in DAC Register Voltage (V)
FFF
4095
–4.9976
801
2049
–2.44E–3
800
2048
0
7FF
2047
+2.44E–3
000 0 +5
To maintain monotonicity and accuracy, R1, R2, and R4 should
be selected to match within 0.01% and must all be of the same
(preferably metal foil) type to assure temperature coefficient
matching. Mismatching between R1 and R2 causes offset and gain
errors while an R4 to R1 and R2 mismatch yields gain errors.
For applications that do not require high accuracy, the circuit
illustrated in Figure 29 can also be used to generate a bipolar
output voltage. In this circuit, only one op amp is used and no
potentiometers are used for offset and gain trim. The output
voltage is coded in offset binary and is given by:
VO = 1 mV × Digital Code ×
R4
R3 + R4
×
1+
R2
R1
–2.5 ×
R2
R1
+5V
0.1µF
CS
CLR
LD
SCLK
SDI
2
REF03
4
R1
6
+2.5V
+5V
0.1µF
1
2 VDD
6 DAC8512 R3
58
3
4 GND
7
R2
+5V
28
A1
34
1
–5V
A1 = 1/2 OP295
R4
VO
VOUT RANGE R1 R2 R3
R4
؎2.5V 10k 10k 10k 15.4k + 274
؎5V 10k 20k 10k 43.2k + 499
Figure 29. Bipolar Output Operation without Trim
For the ± 2.5 V output range and the circuit values shown in the
table, the transfer equation becomes:
VO = 1.22 mV × Digital Code – 2.5 V
Similarly, for the ± 5 V output range, the transfer equation
becomes:
VO = 2.44 mV × Digital Code – 5 V
Generating a Negative Supply Voltage
Some applications may require bipolar output configuration but
only have a single power supply rail available. This is very com-
mon in data acquisition systems using microprocessor-based
systems. In these systems, +12 V, +15 V, and/or +5 V are only
available. Shown in Figure 30 is a method of generating a nega-
tive supply voltage using one CD4049, a CMOS hex inverter,
operating on +12 V or +15 V. The circuit is essentially a charge
pump where two of the six are used as an oscillator. For the val-
ues shown, the frequency of oscillation is approximately 3.5 kHz
and is fairly insensitive to supply voltage because R1 > 2 × R2.
The remaining four inverters are wired in parallel for higher out-
put current. The square wave output is level translated by C2 to
a negative-going signal, rectified using a pair of 1N4001s, and
then filtered by C3. With the values shown, the charge pump
will provide an output voltage of –5 V for current loadings in the
range 0.5 mA ≤ IOUT ≤ 10 mA with a +15 V supply and 0.5 mA
≤ IOUT ≤ 7 mA with a +12 V supply.
INVERTERS = CD4049
3
25
4
R1
510kΩ
R2
5.1kΩ
7
9
11
14
C1
0.02µF
6
10
C2
47µF
D2
1N4001
R3
470Ω
12
–5V
15
D1 C3 1N5231
1N4001 47µF 5.1V
ZENER
Figure 30. Generating a –5 V Supply When Only +12 V
or +15 V Is Available
A High-Compliance, Digitally Controlled Precision Current
Source
The circuit in Figure 31 shows the DAC8512 controlling a
high-compliance precision current source using an AMP05 in-
strumentation amplifier. The AMP05’s reference pin becomes
the input, and the “old” inputs now monitor the voltage across a
precision current sense resistor, RCS. Voltage gain is set to unity,
so the transfer function is given by the following equation:
IOUT
=
VIN
RCS
If RCS equals 100 Ω, the output current is limited to +10 mA
with a 1 V input. Therefore, each DAC LSB corresponds to
2.4 µA. If a bipolar output current is required, then the circuit
in Figure 28 can be modified to drive the AMP05’s reference
pin with a ± 1 V input signal.
Potentiometer P1 trims the output current to zero with the in-
put at 0 V. Fine gain adjustment can be accomplished by adjust-
ing R1 or R2.
REV. A
–11–
11 Page | ||
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