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PDF DAC8420EP Data sheet ( Hoja de datos )

Número de pieza DAC8420EP
Descripción Quad 12-Bit Serial Voltage Output DAC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
Quad 12-Bit Serial
Voltage Output DAC
FEATURES
Guaranteed Monotonic Over Temperature
Excellent Matching Between DACs
Unipolar or Bipolar Operation
Buffered Voltage Outputs
High Speed Serial Digital Interface
Reset to Zero- or Center-Scale
Wide Supply Range, +5 V-Only to ؎15 V
Low Power Consumption (35 mW max)
Available in 16-Pin DIP and SOL Packages
APPLICATIONS
Software Controlled Calibration
Servo Controls
Process Control and Automation
ATE
GENERAL DESCRIPTION
The DAC8420 is a quad, 12-bit voltage-output DAC with serial
digital interface, in a 16-pin package. Utilizing BiCMOS tech-
nology, this monolithic device features unusually high circuit
density and low power consumption. The simple, easy-to-use
serial digital input and fully buffered analog voltage outputs
require no external components to achieve specified performance.
The three-wire serial digital input is easily interfaced to micro-
processors running at 10 MHz rates, with minimal additional
circuitry. Each DAC is addressed individually by a 16-bit serial
word consisting of a 12-bit data word and an address header.
The user-programmable reset control CLR forces all four DAC
outputs to either zero or midscale, asynchronously overriding
the current DAC register values. The output voltage range, de-
termined by the inputs VREFHI and VREFLO, is set by the
user for positive or negative unipolar or bipolar signal swings
within the supplies allowing considerable design flexibility.
DAC8420
FUNCTIONAL BLOCK DIAGRAM
SDI 10
CS 12
CLK 11
NC 13
VREFHI
5
RREEGG DAC A
AA
12
VDD
1
7 VOUTA
SHIFT
REGISTER
REG DAC B
B
6 VOUTB
4
REG DAC C
C
3 VOUTC
LD 14
DECODE
2
REG DAC D
D
2 VOUTD
9
GND
16 15
CLSEL CLR
4
VREFLO
8
VSS
The DAC8420 is available in 16-pin epoxy DIP, cerdip, and
wide-body SOL (small-outline surface mount) packages. Opera-
tion is specified with supplies ranging from +5 V-only to ± 15 V,
with references of +2.5 V to ± 10 V respectively. Power dissipa-
tion when operating from ± 15 V supplies is less than 255 mW
(max), and only 35 mW (max) with a +5 V supply.
For applications requiring product meeting MIL-STD-883,
contact your local sales office for the DAC8420/883 data sheet,
which specifies operation over the –55°C to +125°C tempera-
ture range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

1 page




DAC8420EP pdf
DATA LOAD SEQUENCE
CS
tCSS
SDI A1
A0
X
X D11 D10 D9 D8
DAC8420
tCSH
D4 D3 D2 D1 D0
CLK
LD
tLD1
DATA LOAD TIMING
SDI
tDS tDH
CLK
tCL
CS
LD
VOUT
tCH
tCSH
tLD2
tLDW
tS
CLEAR TIMING
CLSEL
CLR
VOUT
±1LSB
Timing Diagram
tLD2
tCLRW
tS
±1LSB
+15V
1N4001
–10V
1N4001
+10V
1N4001
–15V
1N4001
10
+
10µF
10
+ 10µF
10
+
10µF
10
10µF
+
0.1µF
0.1µF
5k
0.1µF
0.1µF
1
NC 2
NC 3
4
5
NC 6
NC 7
8
DUT
5k
16
15
14
13 NC
12
11
10
9
10k
NC = NO CONNECT
Burn-In Diagram
ORDERING GUIDE
Model1
Temperature
Range
INL
Package
Package
(؎LSB) Description Option2
DAC8420EP
DAC8420EQ
DAC8420ES
DAC8420FP
DAC8420FQ
DAC8420FS
DAC8420QBC
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0.5
0.5
0.5
1.0
1.0
1.0
1.0
Plastic DIP
Cerdip
SOIC
Plastic DIP
Cerdip
SOIC
Dice3
P
Q
SOL
P
Q
SOL
NOTES
1A complete /883 data sheet is available. For availability and burn-in informa-
tion, contact your local sales office.
2PMI division letter designator.
3Dice tested at +25°C only.
REV. 0
–5–

5 Page





DAC8420EP arduino
DAC8420
VREFHI Input Requirements
The DAC8420 utilizes a unique, patented DAC switch driver
circuit which compensates for different supply, reference volt-
age, and digital code inputs. This ensures that all DAC ladder
switches are always biased equally, ensuring excellent linearity
under all conditions. Thus, as indicated in the specifications,
the VREFHI input of the DAC8420 will require both sourcing
and sinking current capability from the reference voltage source.
Many positive voltage references are intended as current sources
only, and offer little sinking capability. The user should consider
references such as the AD584, AD586, AD587, AD588, AD780,
and REF43 in this application.
APPLICATIONS
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The DAC8420 has a single ground pin
that is internally connected to the digital section as the logic
reference level. The first thought may be to connect this pin to
the digital ground; however, in large systems the digital ground
is often noisy because of the switching currents of other digital
circuitry. Any noise that is introduced at the ground pin could
couple into the analog output. Thus, to avoid error causing
digital noise in the sensitive analog circuitry, the ground pin
should be connected to the system analog ground. The ground
path (circuit board trace) should be as wide as possible to re-
duce any effects of parasitic inductance and ohmic drops. A
ground plane is recommended if possible. The noise immunity
of the onboard digital circuitry, typically in the hundreds of mil-
livolts, is well able to reject the common-mode noise typically
seen between system analog and digital grounds. Finally, the
analog and digital ground should be connected together at a
single point in the system to provide a common reference.
This is preferably done at the power supply.
Good grounding practice is essential to maintaining analog
performance in the surrounding analog support circuitry as well.
With two reference inputs, and four analog outputs capable of
moderate bandwidth and output current, there is a significant
potential for ground loops. Again, a ground plane is recom-
mended as the most effective solution to minimizing errors due
to noise and ground offsets.
+VS
10µF
0.1µF
1
VDD
–VS 8 VSS
10µF
0.1µF
GND 9
10µF = TANTALUM
0.1µF = CERAMIC
Figure 26. Recommended Supply Bypassing Scheme
The DAC8420 should have ample supply bypassing, located as
close to the package as possible. Figure 26 shows the recom-
mended capacitor values of 10 µF in parallel with 0.1 µF. The
0.1 µF cap should have low “Effective Series Resistance” (ESR)
and “Effective Series Inductance” (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching. In order to preserve the specified analog perfor-
mance of the device, the supply should be as noise free as pos-
sible. In the case of 5 V only systems it is desirable to use the
same 5 V supply for both the analog circuitry and the digital
portion of the circuit. Unfortunately, the typical 5 V supply is
extremely noisy due to the fast edge rates of the popular CMOS
logic families which induce large inductive voltage spikes, and
busy microcontroller or microprocessor busses which commonly
have large current spikes during bus activity. However, by prop-
erly filtering the supply as shown in Figure 27, the digital 5 V
supply can be used. The inductors and capacitors generate a fil-
ter that not only rejects noise due to the digital circuitry, but
also filters out the lower frequency noise of switch mode power
supplies. The analog supply should be connected as close as
possible to the origin of the digital supply to minimize noise
pickup from the digital section.
TTL/CMOS
LOGIC
CIRCUITS
FERRITE BEADS:
2 TURNS, FAIR-RITE
#2677006301
+5V
100µF
ELECT.
10–22µF
TANT.
0.1µF
CER.
+5V
POWER SUPPLY
+5V
RETURN
Figure 27. Single-Supply Analog Supply Filter
Analog Outputs
The DAC8420 features buffered analog voltage outputs capable
of sourcing and sinking up to 5 mA when operating from ± 15 V
supplies, eliminating the need for external buffer amplifiers in
most applications while maintaining specified accuracy over the
rated operating conditions. The buffered outputs are simply an
op amp connected as a voltage follower, and thus have output
characteristics very similar to the typical operational amplifier.
These amplifiers are short-circuit protected. The designer
should verify that the output load meets the capabilities of the
device, in terms of both output current and load capacitance.
The DAC8420 is stable with capacitive loads up to 2 nF typical.
However, any capacitive load will increase the settling time, and
should be minimized if speed is a concern.
The output stage includes a p-channel MOSFET to pull the
output voltage down to the negative supply. This is very impor-
tant in single supply systems, where VREFLO usually has the
same potential as the negative supply. With no load, the
zero-scale output voltage in these applications will be less than
500 µV typically, or less than 1 LSB when VVREFHI = 2.5 V.
However, when sinking current this voltage does increase
because of the finite impedance of the output stage. The effec-
tive value of the pull-down resistor in the output stage is
typically 320 . With a 100 kresistor connected to +5 V, the
resulting zero-scale output voltage is 16 mV. Thus, the best
REV. 0
–11–

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