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PDF DAC8248FP Data sheet ( Hoja de datos )

Número de pieza DAC8248FP
Descripción Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
Dual 12-Bit (8-Bit Byte)
Double-Buffered CMOS D/A Converter
DAC8248
FEATURES
Two Matched 12-Bit DACs on One Chip
12-Bit Resolution with an 8-Bit Data Bus
Direct Interface with 8-Bit Microprocessors
Double-Buffered Digital Inputs
RESET to Zero Pin
12-Bit Endpoint Linearity (؎1/2 LSB) Over Temperature
؉5 V to ؉15 V Single Supply Operation
Latch-Up Resistant
Improved ESD Resistance
Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin
SOL Package
Available in Die Form
PIN CONNECTIONS
24-Pin 0.3" Cerdip (W Suffix),
24-Pin Epoxy DIP (P Suffix),
24-Pin SOL (S Suffix)
APPLICATIONS
Multichannel Microprocessor-Controlled Systems
Robotics/Process Control/Automation
Automatic Test Equipment
Programmable Attenuator, Power Supplies, Window
Comparators
Instrumentation Equipment
Battery Operated Equipment
GENERAL DESCRIPTION
The DAC8248 is a dual 12-bit, double-buffered, CMOS digital-
to-analog converter. It has an 8-bit wide input data port that inter-
faces directly with 8-bit microprocessors. It loads a 12-bit word in
two bytes using a single control; it can accept either a least signifi-
cant byte or most significant byte first. For designs with a 12-bit or
16-bit wide data path, choose the DAC8222 or DAC8221.
The DAC8248’s double-buffered digital inputs allow both
DAC’s analog output to be updated simultaneously. This is par-
ticularly useful in multiple DAC systems where a common
LDAC signal updates all DACs at the same time. A single
RESET pin resets both outputs to zero.
The DAC8248’s monolithic construction offers excellent DAC-
to-DAC matching and tracking over the full operating tempera-
ture range. The DAC consists of two thin-film R-2R resistor
ladder networks, two 12-bit, two 8-bit, and two 4-bit data regis-
ters, and control logic circuitry. Separate reference input and
feedback resistors are provided for each DAC. The DAC8248
(continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

1 page




DAC8248FP pdf
DICE CHARACTERISTICS
DAC8248
11. AGND
12. IOUTA
13. RFB A
14. VREF A
15. DGND
16. DB7(MSB)
17. DB6
18. DB5
13. NC
14. DB1
15. DB0(LSB)
16. RESET
17. LSB/MSB
18. DAC A/DAC B
19. LDAC
20. WR
19. DB4
10. DB3
11. DB2
12. NC
21. VDD
22. VREF B
23. RFB B
24. IOUT B
SUBSTRATE (DIE BACKSIDE) IS INTERNALLY
CONNECTED TO VDD.
Die Size 0.124 × 0.132 inch, 16,368 sq. mils
(3.15 × 3.55 mm, 10.56 sq. mm)
WAFER TEST LIMITS @ VDD = +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = 25؇C.
Parameter
Symbol
Conditions
DAC8248G
Limit
Units
Relative Accuracy
Differential Nonlinearity
Full-Scale Gain Error1
Output Leakage
(IOUT A, IOUT B)
Input Resistance
(VREF A, VREF B)
VREF A, VREF B Input
Resistance Match
Digital Input High
Digital Input Low
Digital Input Current
Supply Current
DC Supply Rejection
(Gain/VDD)
INL
DNL
GFSE
ILKG
RREF
RREF
RREF
VINH
VINL
IIN
IDD
PSR
Endpoint Linearity Error
All Grades are Guaranteed Monotonic
Digital Inputs = 1111 1111 1111
Digital Inputs = 0000 0000 0000
Pads 2 and 24
Pads 4 and 22
VDD = +5 V
VDD = +15 V
VDD = +5 V
VDD = +15 V
VIN = 0 V or VDD; VINL or VINH
All Digital Inputs VINL or VINH
All Digital Inputs 0 V or VDD
VDD = ± 5%
±1
±1
±4
± 50
8/15
±1
2.4
13.5
0.8
1.5
±1
2
0.1
0.002
LSB max
LSB max
LSB max
nA max
kmin/kmax
% max
V min
V min
V max
V max
µA max
mA max
mA max
%/% max
NOTES
1Measured using internal RFB A and RFB B.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
–5–

5 Page





DAC8248FP arduino
DAC8248
AUTOMATIC DATA TRANSFER MODE
Data may be transferred automatically from the input register to
the DAC register. The first cycle loads the first data byte into
the input register; the second cycle loads the second data byte
and simultaneously transfers the full 12-bit data word to the
DAC register. It takes four cycles to load and transfer two com-
plete digital words for both DAC’s, see Figure 4 (Four Cycle
Update Timing Diagram) and the Mode Selection Table.
STROBED DATA TRANSFER MODE
Strobed data transfer allows the full 12-bit digital word to be
loaded into the input registers and transferred to the DAC regis-
ters at a later time. This transfer mode requires five cycles: four
to load two new data words into both DACs, and the fifth to
transfer all data into the DAC registers. See Figure 5 (Five Cycle
Update Timing Diagram) and the Mode Selection Table.
Strobed data transfer separating data loading and transfer op-
erations serves two functions: the DAC output updating may be
more precisely controlled, and multiple DACs in a multiple
DAC system can be updated simultaneously.
RESET
The DAC8248 comes with a RESET pin that is useful in system
calibration cycles and/or during system power-up. All registers
are reset to zero when RESET is low, and latched at zero on the
rising edge of the RESET signal when WRITE is high.
INTERFACE CONTROL LOGIC
The DAC8248’s control logic is shown in Figure 6. This cir-
cuitry interfaces with the system bus and controls the DAC
functions.
Figure 6. Input Control Logic
MODE SELECTION TABLE
DIGITAL INPUTS
DAC A/B WR LSB/MSB RESET
LDAC
REGISTER STATUS
DAC A
DAC B
Input Register
DAC
Input Register
LSB MSB Register LSB MSB
L
LL
H
H WR
LAT
LAT
LAT
LAT
L
LL
H
L
WR
LAT
WR
LAT
LAT
L
LH
H
H LAT WR LAT
LAT
LAT
L
LH
H
L LAT WR WR
LAT
LAT
H
LL
H
H
LAT
LAT
LAT
WR
LAT
H
LL
H
L
LAT
LAT
WR
WR LAT
H
LH
H
H
LAT
LAT
LAT
LAT
WR
H
LH
H
L
LAT
LAT
WR
LAT
WR
X
HX
H
H
LAT
LAT
LAT
LAT
LAT
X
HX
H
L
LAT
LAT
WR
LAT
LAT
X X X L X ALL REGISTERS ARE RESET TO ZEROS
X H X g X ZEROS ARE LATCHED IN ALL REGISTERS
L = Low, H = High, X = Don’t Care, WR = Registers Being Loaded, LAT = Registers Latched.
DAC
Register
LAT
WR
LAT
WR
LAT
WR
LAT
WR
LAT
WR
REV. B
–11–

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