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Número de pieza DAC8143FS
Descripción 12-Bit Serial Daisy-Chain CMOS D/A Converter
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
12-Bit Serial Daisy-Chain
CMOS D/A Converter
DAC8143
FEATURES
Fast, Flexible, Microprocessor Interfacing in Serially
Controlled Systems
Buffered Digital Output Pin for Daisy-Chaining
Multiple DACs
Minimizes Address-Decoding in Multiple DAC
Systems—Three-Wire Interface for Any Number of DACs
One Data Line
One CLK Line
One Load Line
Improved Resistance to ESD
–40؇C to +85؇C for the Extended Industrial Temperature
Range
APPLICATIONS
Multiple-Channel Data Acquisition Systems
Process Control and Industrial Automation
Test Equipment
Remote Microprocessor-Controlled Systems
GENERAL INFORMATION
The DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A
converter that features serial data input and buffered serial data
output. It was designed for multiple serial DAC systems, where
serially daisy-chaining one DAC after another is greatly simplified.
The DAC8143 also minimizes address decoding lines enabling
simpler logic interfacing. It allows three-wire interface for any
number of DACs: one data line, one CLK line and one load line.
Serial data in the input register (MSB first) is sequentially
clocked out to the SRO pin as the new data word (MSB first) is
simultaneously clocked in from the SRI pin. The strobe inputs
are used to clock in/out data on the rising or falling (user
selected) strobe edges (STB1, STB2, STB3, STB4).
When the shift register’s data has been updated, the new data
word is transferred to the DAC register with use of LD1 and
LD2 inputs.
Separate LOAD control inputs allow simultaneous output up-
dating of multiple DACs. An asynchronous CLEAR input
resets the DAC register without altering data in the input
register.
Improved linearity and gain error performance permits reduced
circuit parts count through the elimination of trimming compo-
nents. Fast interface timing reduces timing design considerations
while minimizing microprocessor wait states.
The DAC8143 is available in plastic packages that are compat-
ible with autoinsertion equipment.
Plastic packaged devices come in the extended industrial tem-
perature range of –40°C to +85°C.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
VREF
CLR
LD1
LD2
STB1
STB4
STB3
STB2
SRI
FUNCTIONAL BLOCK DIAGRAM
VDD
DAC8143
12-BIT
D/A CONVERTER
DAC REGISTER
LOAD
RFB
IOUT1
IOUT2
AGND
CLK
INPUT 12-BIT
SHIFT REGISTER
IN OUT
DGND
SRO
WR
DBX
P
ADDRESS BUS
ADDRESS
DECODER
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
Figure 1. Multiple DAC8143s with Three-Wire Interface
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

1 page




DAC8143FS pdf
Typical Performance Characteristics–DAC8143
ALL BITS ON
(MSB) B11
B10
B9
B8
DATA BITS "ON" B7
(ALL OTHER
B6
DATA BITS "OFF") B5
B4
B3
B2
B1
(LSB) B0
0
12
24
36
48
60
72
84
96
108
100 1k 10k 100k 1M 10M
FREQUENCY – Hz
Figure 2. Multiplying Mode Frequency
Response vs. Digital Code
–70
VIN = 5V rms
OUTPUT OP AMP: OP-42
–75
0.032
0.018
–80 0.010
–85 0.0056
–90 0.0032
–95
10
100 1k 10k
FREQUENCY – Hz
0.0018
100k
Figure 3. Multiplying Mode Total Harmonic
Distortion vs. Frequency
3
2
1
0
012 3 45
VIN – Volts
Figure 4. Supply Current vs. Logic
Input Voltage
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4095
DIGITAL INPUT CODE – Decimal
Figure 5. Linearity Error vs. Digital
Code
0.5
0.25
0
–0.25
–0.5
2
46
8
VREF – Volts
10
Figure 6. Linearity Error vs. Refer-
ence Voltage
4
3
2.4
2
1
–0.8
0
1 3 5 7 9 11 13 15 17
VDD – Volts
Figure 7. Logic Threshold Voltage
vs. Supply Voltage
0.5
0.25
0
–0.25
–0.5
2
46
8
VREF – Volts
10
Figure 8. DNL Error vs. Reference
Voltage
40
TA = +25؇C
30
20
LOGIC 0
10
0
–10
LOGIC 1
–20
–30
–40
0
12 3 4
SRO – VOLTAGE OUT – Volts
5
Figure 9. Digital Output Voltage vs.
Output Current
REV. C
–5–

5 Page





DAC8143FS arduino
DAC8143
ADDRESS BUS
WR
ADDRESS
DECODER
DBX SRI STROBE
DAC8143
SRO LOAD
P
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
SRI STROBE
DAC8143
SRO LOAD
Figure 19. Multiple DAC8143s with Three-Wire Interface
ANALOG/DIGITAL DIVISION
The transfer function for the DAC8143 connect in the multiply-
ing mode as shown in Figures 16 and 17 is:
VO = –VIN

A1
21
+
A2
22
+
A3
23
+
.
.
.
A12
212

where AX assumes a value of 1 for an “ON” bit and 0 for an
“OFF” bit.
The transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 20
and is:

VIN
VO
=

A1
21
+
A2
22
+
A3
23
+
.
.
.
A12
212

The above transfer function is the division of an analog voltage
(VREF) by a digital word. The amplifier goes to the rails with all
bits “OFF” since division by zero is infinity. With all bits “ON”
the gain is 1 (± 1 LSB). The gain becomes 4096 with the LSB,
Bit 12, “ON”.
DIGITAL
INPUTS
4 13
VIN 16 RFB
VDD 14 +5V
6
SRO
BUFFERED DIGITAL
1
DAC8143
IOUT1
VREF
15
DATA OUT
AGND 3 2 12 DGND
2–
OP-42
3+
6
VOUT
APPLICATION TIPS
In most applications, linearity depends on the potential of IOUT1,
IOUT2, and AGND (Pins 1, 2 and 3) being exactly equal to each
other. In most applications, the DAC is connected to an exter-
nal op amp with its noninverting input tied to ground (see Fig-
ures 16 and 17). The amplifier selected should have a low input
bias current and low drift over temperature. The amplifier’s
input offset voltage should be nulled to less than ± 200 µV (less
than 10% of 1 LSB).
The operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias cur-
rent compensation resistor should not be used. This resistor can
cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The VDD power supply should
have a low noise level with no transients greater than +17 V.
It is recommended that the digital inputs be taken to ground or
VDD via a high value (1 M) resistor; this will prevent the accu-
mulation of static charge if the PC card is disconnected from the
system.
Peak supply current flows as the digital input pass through the
transition region (see Figure 4). The supply current decreases as
the input voltage approaches the supply rails (VDD or DGND),
i.e., rapidly slewing logic signals that settle very near the supply
rails will minimize supply current.
INTERFACING TO THE MC6800
As shown in Figure 21, the DAC8143 may be interfaced to the
6800 by successively executing memory WRITE instruction
while manipulating the data between WRITEs, so that each
WRITE presents the next bit.
In this example, the most significant bits are found in memory
locations 0000 and 0001. The four MSBs are found in the lower
half of 0000, the eight LSBs in 0001. The data is taken from the
DB7 line.
The serial data loading is triggered by STB4 which is asserted by
a decoded memory WRITE to a memory location, R/W, and
Φ2. A WRITE to another address location transfers data from
input register to DAC register.
A0
A15
MC6800
R/W
φ2
16-BIT ADDRESS BUS
E1 A0 A2
E3
74LS138
ADDRESS
E2 DECODER
DB0
DB7
+5V
8-BIT DATA BUS
SRI
STB3
LD1
STB2
STB4
LD2 STB1
DAC8143*
SRO
CLR
FROM SYSTEM RESET
*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY
Figure 21. DAC8143—MC6800 Interface
REV. C
Figure 20. Analog/Digital Divider
–11–

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