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PDF DAC7802L Data sheet ( Hoja de datos )

Número de pieza DAC7802L
Descripción Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
Fabricantes Burr-Brown Corporation 
Logotipo Burr-Brown Corporation Logotipo



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® DAC7800
DAC7801
DAC7802
Dual Monolithic CMOS 12-Bit Multiplying
DIGITAL-TO-ANALOG CONVERTERS
FEATURES
q TWO D/As IN A 0.3" WIDE PACKAGE
q SINGLE +5V SUPPLY
q HIGH SPEED DIGITAL INTERFACE:
Serial—DAC7800
8 + 4-Bit Parallel—DAC7801
12-Bit Parallel—DAC7802
q MONOTONIC OVER TEMPERATURE
q LOW CROSSTALK: –94dB min
q FULLY SPECIFIED OVER –40OC TO +85OC
APPLICATIONS
q PROCESS CONTROL OUTPUTS
q ATE PIN ELECTRONICS LEVEL SETTING
q PROGRAMMABLE FILTERS
q PROGRAMMABLE GAIN CIRCUITS
q AUTO-CALIBRATION CIRCUITS
DESCRIPTION
The DAC7800, DAC7801 and DAC7802 are mem-
bers of a new family of monolithic dual 12-bit CMOS
multiplying digital-to-analog converters. The digital
interface speed and the AC multiplying performance
are achieved by using an advanced CMOS process
optimized for data conversion circuits. High stability
on-chip resistors provide true 12-bit integral and dif-
ferential linearity over the wide industrial temperature
range of –40oC to +85oC.
DAC7800 features a serial interface capable of clock-
ing-in data at a rate of at least 10MHz. Serial data is
clocked (edge triggered) MSB first into a 24-bit shift
register and then latched into each D/A separately or
simultaneously as required by the application. An
asynchronous CLEAR control is provided for power-
on reset or system calibration functions. It is packaged
in a 16-pin 0.3" wide plastic DIP.
DAC7801 has a 2-byte (8 + 4) double-buffered
interface. Data is first loaded (level transferred) into
the input registers in two steps for each D/A. Then
both D/As are updated simultaneously. DAC7801 fea-
tures an asynchronous CLEAR control. DAC7801 is
packaged in a 24-pin 0.3" wide plastic DIP.
DAC7802 has a single-buffered 12-bit data word in-
terface. Parallel data is loaded (edge triggered) into the
single D/A register for each D/A. DAC7802 is pack-
aged in a 24-pin 0.3" wide plastic DIP.
DAC7802
12 12-Bit Interface
DAC7801
8 8-Bit Interface
8 Bits + 4 Bits
Serial
DAC7800
Serial Interface
VREF A
12 12-Bit MDAC
DAC A
RFB A
IOUT A
AGND A
VREF B
12 12-Bit MDAC
DAC B
RFB B
IOUT B
AGND B
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-11079G
DAC7800Pr,int0ed1in,U0.S.2A. January, 1998
®

1 page




DAC7802L pdf
DAC7800 (CONT)
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.
t5
PARAMETER
t1 — Data Setup Time
t2 — Data Hold Time
t3 — Chip Select to CLK,
Update, Data Setup Time
t4 — Chip Select to CLK,
Update, Data Hold Time
t5 — CLK Pulse Width
t6 — Clear Pulse Width
t7 — Update Pulse Width
t8 — CLK Edge to UPD A
or UPD B
MINIMUM
15ns
15ns
15ns
40ns
40ns
40ns
40ns
15ns
CLK
DATA
CS
UPD A
UPD B
CLR
t3
t1
t2
t8 t7 t4
0V
5V
0V
5V
5V
t6
5V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. tR = tF = 5ns. (2) Tim-
ing measurement reference level is VIH + V IL .
2
DAC7801
BLOCK DIAGRAM
VDD
20
DAC7801
UPD 19
A1 16
A0 15
CS 5
WR 18
CLR 17
DAC A
MS
Input
Reg
DAC A
LS
Input
Reg
48
DAC A Register
12
DAC A
DAC B
12
DAC B Register
48
DAC B
MS
Input
Reg
DAC B
LS
Input
Reg
2 IOUT A
1 AGND A
3 RFB A
4 V REF A
21 V REF B
22 RFB B
23 IOUT B
24 AGND B
PIN CONFIGURATION
AGND A 1
IOUT A
RFB A
VREF A
CS
2
3
4
5
DB0 6
DB1 7
DB2 8
DB3 9
DB4 10
DB5 11
DGND 12
DAC7801
Top View
DIP
24 AGND B
23 IOUT B
22 RFB B
21 VREF B
20 VDD
19 UPD
18 WR
17 CLR
16 A1
15 A0
14 DB7
13 DB6
14 6
DB7–DB0
LOGIC TRUTH TABLE
CLR
UPD
CS
11
11
0X
11
11
11
11
10
10
1
X
X
0
0
0
0
1
0
X = Don’t care.
12
DGND
WR A1
XX
1X
XX
00
00
01
01
0X
0X
A0 FUNCTION
X No Data Transfer
X No Data Transfer
X All Registers Cleared
0 DAC A LS Input Register Loaded with DB7–DB0 (LSB)
1 DAC A MS Input Register Loaded with DB3 (MSB)–DB0
0 DAC B LS Input Register Loaded with DB7–DB0 (LSB)
1 DAC B MS Input Register Loaded with DB3 (MSB)–DB0
X DAC A, DAC B Registers Updated Simultaneously from Input Registers
X DAC A, DAC B Registers are Transparent
®
5 DAC7800, 01, 02

5 Page





DAC7802L arduino
CD +
1µF
+5V
VDD VIN A
R1
100
VREF A
DAC A
DAC7802
DAC B
R6
20k
RFB A
R2
47
IOUT A
AGND A
RFB B
R4
47
IOUT B
AGND B
DGND
VREF B
R3
100
R10
20k
VIN B
R5
20k
R7
10k
A2
+
VOUT A
C1
10pF
A1
+
DAC7802 has a single analog common, AGND.
A1–A4, OPA602 or 1/2 OPA2107.
C2
10pF
A3
+
R9
10k
R8
20k
A4
+
VOUT B
FIGURE 6. Bipolar Configuration with Gain Trim.
+10V
CD
1µF
+15V
+5V
VDD
2
6 REF102
4
VREF A
RFB A
DAC A
IOUT A
AGND A
C1
10pF
A1
DAC780X
DAC B
AGND B
Sign Control
DG188
R
2
R
3
R
1
R
±10V
6 13 Bits
INA105
DGND
VREF B
FIGURE 7. 12-Bit Plus Sign DAC.
DAC7802 has a single analog common, AGND.
A1 OPA602 or 1/2 OPA2107.
®
11 DAC7800, 01, 02

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