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PDF 10020EV8-4A Data sheet ( Hoja de datos )

Número de pieza 10020EV8-4A
Descripción ECL programmable array logic
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
Product specification
10H20EV8/10020EV8
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL® device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
Semiconductors simplifies design entry
based upon Boolean or state equations.
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR’d
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn’t in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
FEATURES
Ultra high speed ECL device
tPD = 4.5ns (max)
tIS = 2.6ns (max)
tCKO = 2.3ns (max)
fMAX = 208MHz
Universal ECL Programmable Array Logic
8 user programmable output macrocells
Up to 20 inputs and 8 outputs
Individual user programmable output
polarity
Variable product term distribution allows
increased design capability
Asynchronous Preset and Reset capability
10KH and 100K options
Power-up Reset and Preload function to
enhance state machine design and testing
Design support provided via SNAP and
other CAD tools
Security fuse for preventing design
duplication
Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
PIN CONFIGURATIONS
F Package
I1 1
I2 2
CLK/I12 3
F1 4
F2 5
VCO1 6
F3 7
F4 8
I3 9
I4 10
I5 11
VEE 12
F = Ceramic DIP (300mil-wide)
24 VCC
23 I11
22 I10
21 F8
20 F7
19 VCO2
18 F6
17 F5
16 I9
15 I8
14 I7
13 I6
A Package
CLK/I12 I2 I1 NC VCC I11 I10
4 3 2 1 28 27 26
F1 5
F2 6
VCO1 7
NC 8
25 F8
24 F7
23 VCO2
22 NC
F3 9
21 F6
F4 10
20 F5
I3 11
19 I9
12 13 14 15 16 17 18
I4 I5 VEE NC I6 I7 I8
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line (300mil-wide)
28-Pin Plastic Leaded Chip Carrier
ORDER CODE
10H20EV8–4F
10020EV8–4F
10H20EV8–4A
10020EV8–4A
DRAWING NUMBER
0586B
0401F
®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
October 22, 1993
113
853–1423 11164

1 page




10020EV8-4A pdf
Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
D
AP
DQ
CK Q
AR
Registered Active-HIGH
D
Product specification
10H20EV8/10020EV8
D
AP
DQ
CK Q
AR
Registered Active-LOW
D
Combinatorial Active-HIGH
Combinatorial Active-LOW
Figure 2. Output Macro Cell Configurations
OUTPUT MACRO CELL
CONFIGURATION
Shown in Figure 2 are the four possible
configurations of the output macrocell using
fuses S0 and S1. As seen, the output can
either be registered Active-HIGH/LOW with
feedback or combinatorial Active-HIGH/LOW
with feedback. If the registered mode is
chosen, the feedback from the Q output to
the AND array enables one to make state
machines or shift registers without having to
tie the output to one of the inputs. If a
combinatorial output is chosen, the feedback
gate is enabled from the pin and allows one
to create permanent outputs, permanent
inputs, or I/O pins through the use of the
output enable (D) product term.
OUTPUT ENABLE
Each output on the 10H20EV8/10020EV8
has its own individual product term for output
enable. The use of the D product term
(direction control) allows the user three
possible configurations of the outputs. They
are: always enabled, always disabled, and
controlled by a programmed pattern. A HIGH
on the D term enables the output, while a
LOW performs the disable function. Output
enable control can be achieved by
programming a pattern on the D term.
The output enable control can also be used
to expand a designer’s possibilities once a
combinatorial output has been chosen. If the
D term is always HIGH, the pin becomes a
permanent Active-HIGH/LOW output. If the
D term is always LOW (all fuses left intact),
the pin now becomes an extra input.
PRESET AND RESET
The 10H20EV8/10020EV8 also includes a
separate product term for asynchronous
Preset and asynchronous Reset. These lines
are common for all registers and are asserted
when the specific product term goes HIGH.
Being asynchronous, they are independent of
the clock. It should be noted that the actual
state of the output is dependent on how the
polarity of the particular output has been
chosen. If the outputs are a mix of
Active-HIGH and Active-LOW, a Preset
signal will force the Active-HIGH outputs
HIGH while the Active-LOW outputs would go
LOW, even though the Q output of all
flip-flops would go HIGH. A Reset signal
would force the opposite conditions.
PRELOAD
To simplify testing, the 10H20EV8/10020EV8
has also included PRELOAD circuitry. This
allows a user to load any particular data
desired into the registers regardless of the
programmed pattern. This means that the
PRELOAD can be done on a blank part and
after that same part has been programmed to
facilitate any post-fuse testing desired.
It can also be used by a designer to help
debug a circuit. This could be important if a
state machine was implemented in the
10H20EV8/ 10020EV8. The PRELOAD
would allow the entry of any state in the
sequence desired and start clocking from that
particular point. Any or all transitions could be
verified.
October 22, 1993
117

5 Page





10020EV8-4A arduino
Philips Semiconductors Programmable Logic Devices
ECL programmable array logic
Product specification
10H20EV8/10020EV8
TIMING DIAGRAMS
I, I/O
(INPUT)
CLK
I/O
(REGISTERED
OUTPUT)
I/O
(COMBINATORIAL
OUTPUT)
50%
tIS
50%
tIH
50%
tCKH
tCKO
50%
tCK
P
50%
tCKL
tPD
50%
Flip-Flop and Gate Outputs
0V
REGISTERED
ACTIVE-LOW
OUTPUT
VEE = –4.94 10H20EV8
VEE = –4.2 10020EV8
VEE
tPPR
50%
I, I/O
(INPUT)
50%
tIS
tCLK
50%
50%
Power-On Reset
October 22, 1993
123

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