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PDF AN1034 Data sheet ( Hoja de datos )
| Número de pieza | AN1034 | |
| Descripción | Analog Switch and Multiplexer Applications | |
| Fabricantes | Intersil Corporation | |
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AN101
An Introduction to FETs
Introduction
The basic principle of the field-effect transistor (FET) has
been known since J. E. Lilienfeld’s patent of 1925. The
theoretical description of a FET made by Shockley in
1952 paved the way for development of a classic electron-
ic device which provides the designer the means to ac-
complish nearly every circuit function. At one time, the
field-effect transistor was known as a “unipolar” transis-
tor. The term refers to the fact that current is transported
by carriers of one polarity (majority), whereas in the con-
ventional bipolar transistor carriers of both polarities
(majority and minority) are involved.
This Application Note provides an insight into the nature of
the FET, and touches briefly on its basic characteristics, ter-
minology, parameters, and typical applications.
The following list of FET applications indicates the ver-
satility of the FET family:
Amplifiers
S Small Signal
S Low Distortion
S High Gain
S Low Noise
S Selectivity
S DC
Switches
S Chopper-Type
S Analog Gate
S Communicator
Protection Diodes
S Low-leakage
S High-Frequency
Current Limiters
Voltage-Controlled Resistors
Mixers
Oscillators
The family tree of FET devices (Figure 1) may be divided
into two main branches, Junction FETs (JFETs) and Insu-
lated Gate FETs (or MOSFETs, metal-oxide- semicon-
ductor field-effect transistors). Junction FETs are in-
herently depletion-mode devices, and are available in
both n- and p-channel configurations. MOSFETs are
available in both enhancement and depletion modes, and
also exist as both n- and p-channel devices. The two main
FET groups depend on different phenomena for their op-
eration, and will be discussed separately.
Junction FETs
In its most elementary form, this transistor consists of a
piece of high-resistivity semiconductor material (usually
silicon) which constitutes a channel for the majority carri-
er flow. The magnitude of this current is controlled by a
voltage applied to a gate, which is a reverse-biased pn
junction formed along the channel. Implicit in this de-
scription is the fundamental difference between JFET and
bipolar devices: when the JFET junction is reverse-biased
the gate current is practically zero, whereas the base cur-
rent of the bipolar transistor is always some value greater
than zero. The JFET is a high-input resistance device,
while the input resistance of the bipolar transistor is com-
paratively low. If the channel is doped with a donor impu-
rity, n-type material is formed and the channel current
will consist of electrons. If the channel is doped with an
acceptor impurity, p-type material will be formed and the
channel current will consist of holes. N-channel devices
have greater conductivity than p-channel types, since
electrons have higher mobility than do holes; thus n-chan-
nel JFETs are approximately twice as efficient conductors
compared to their p-channel counterparts.
FETs
Junction
MOS
Depletion
np
Enhancement
Not Possible
Depletion
np
Figure 1. FET Family Tree
Enhancement
np
Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70594.
Siliconix
10-Mar-97
1
1 page  
AN101
There are three types of small-signal MOSFETs. First, we
have the planar, lateral MOSFET, similar to that shown in
Figure 6a. By virtue of the n-doped channel spanning
from source to drain, it performs as an n-channel deple-
tion-mode MOSFET in a fashion not unlike that of the
depletion-mode JFET when a voltage of the correct polar-
ity is applied to the gate, as in Figure 6b. However, if we
forward-bias the gate (that is, place a gate voltage whose
polarity equals the drain voltage polarity) additional elec-
trons will be attracted to the region beneath the gate, fur-
ther enhancing – and inverting (from p to n) the region.
As the channel region thickens, the channel resistance
will further decrease, allowing greater channel current to
flow beyond that identified as IDSS, as we see in the family
of output characteristics in Figure 6c.
MOSFETs can also be constructed for enhancement -
mode-only performance, as shown in Figure 7. Unlike the
depletion-mode device, the enhancement-mode MOSFET
offers no channel between the source and drain. Not until a
forward bias on the gate enhances a channel by attracting
electrons beneath the gate oxide will current begin to flow
(Figure 6d).
Gate
Source
Drain
ÉÉÉÉÉÉÉÉÉÉÉÉOÉÉxideÉÉÉÉÉÉÉÉÉÉÉÉ
NN
P-Silicon
Body
Figure 7. Planar Enhancement-Mode MOS Cross-Section
A newer MOSFET offering superior performance is the
lateral double-diffused or DMOS FET. Because of the li-
mitations of photo-lithographic masking, the earlier, old-
er-style MOSFET was severely limited in performance.
Some of these former limitations involved switching
speeds, channel conductivity (too high an rDS), and cur-
rent handling in general. The lateral DMOS FET removed
these limitations, offering a viable alternative between
the JFET and the GaAs FET for video and high-speed
switching applications.
The lateral DMOS FET differs radically in its channel
construction when compared with the older planar MOS-
FET. Note the double-diffused source implant into the im-
planted p-doped channel region, shown in Figure 8. The
improved performance of DMOS is a result of both the
precisely-defined short channel that results and the “drift
region” resulting from the remaining p-doped silicon
body and light n-doped ion implant.
Gate
ÉÉSÉÉourcÉÉe ÉÉÉÉÉÉOxMiÉÉdeetal ÉÉÉÉDÉÉrainÉÉÉÉÉÉ
N+ N+
P N–
P-Silicon
Substrate
Figure 8. Planar Enhancement-Mode DMOS
Although Figures 7 and 8 illustrate n-channel enhance-
ment-mode DMOS FETs, by reversing the doping se-
quences, p-channel DMOS FETs can easily be fabricated.
Furthermore, by lightly doping across the short channel
and drift region, depletion-mode DMOS FETs can be
constructed.
As a result of the short channel, the MOSFET is allowed
to operate in “velocity saturation” and as a result of the
drift region, the MOSFET offers higher operating volt-
ages. Together, the short channel and the drift region offer
low on-resistance and low interelectrode capacitances,
especially gate-to-drain, VGD.
Velocity saturation coupled with low interelectrode ca-
pacitance offers us high-speed and high-frequency per-
formance.
Gate N–
ÉÉÉÉÉÉÉSoÉurce
N– P+
P+
Metal
N+
Drain
Figure 9. Vertical N-Channel Enhancement-Mode
DMOS FET
The novelty of the short-channel DMOS FET led to the
evolution of a yet more advanced, higher-voltage, higher-
current MOSFET: the Vertical Double-Diffused MOSFET
(Figure 9). Where this vertical MOSFET offers improved
power-handling capabilities, its fundamental shortcoming is
that because of its construction and to a lesser extent because
of its size, it fails to challenge the high-speed performance
of the lateral DMOS FET. Consequently, the vertical and lat-
eral DMOS FETs complement each other in a wide selection
of applications.
Siliconix
10-Mar-97
5
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