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PDF ADC0808CJ Data sheet ( Hoja de datos )

Número de pieza ADC0808CJ
Descripción 8-Bit uP Compatible A/D Converters with 8-Channel Multiplexer
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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October 1999
ADC0808/ADC0809
8-Bit µP Compatible A/D Converters with 8-Channel
Multiplexer
General Description
The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital con-
verter, 8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive ap-
proximation as the conversion technique. The converter fea-
tures a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a succes-
sive approximation register. The 8-channel multiplexer can
directly access any of 8-single-ended analog signals.
The device eliminates the need for external zero and
full-scale adjustments. Easy interfacing to microprocessors
is provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE® outputs.
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, ex-
cellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally
suited to applications from process and machine control to
consumer and automotive applications. For 16-channel mul-
tiplexer with common output (sample/hold port) see
ADC0816 data sheet. (See AN-247 for more information.)
Features
n Easy interface to all microprocessors
n Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
n No zero or full-scale adjust required
n 8-channel multiplexer with address logic
n 0V to 5V input range with single 5V power supply
n Outputs meet TTL voltage level specifications
n Standard hermetic or molded 28-pin DIP package
n 28-pin molded chip carrier package
n ADC0808 equivalent to MM74C949
n ADC0809 equivalent to MM74C949-1
Key Specifications
n Resolution
n Total Unadjusted Error
n Single Supply
n Low Power
n Conversion Time
8 Bits
±12 LSB and ±1 LSB
5 VDC
15 mW
100 µs
Block Diagram
See Ordering
Information
TRI-STATE® is a registered trademark of National Semiconductor Corp.
© 1999 National Semiconductor Corporation DS005672
DS005672-1
www.national.com

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ADC0808CJ pdf
Functional Description
Multiplexer. The device contains an 8-channel single-ended
analog signal multiplexer. A particular input channel is se-
lected by using the address decoder. Table 1 shows the input
states for the address lines to select any channel. The ad-
dress is latched into the decoder on the low-to-high transition
of the address latch enable signal.
TABLE 1.
SELECTED
ANALOG
CHANNEL
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
ADDRESS LINE
CBA
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive ap-
proximation register, and the comparator. The converter’s
digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems. A non-monotonic relationship can cause os-
cillations that will be catastrophic for the system. Additionally,
the 256R network does not cause load variations on the ref-
erence voltage.
The bottom resistor and the top resistor of the ladder net-
work in Figure 1 are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transi-
tion occurs when the analog signal has reached +12 LSB
and succeeding output transitions occur every 1 LSB later up
to full-scale.
The successive approximation register (SAR) performs 8 it-
erations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2 shows a typical example of a 3-bit converter. In the
ADC0808, ADC0809, the approximation technique is ex-
tended to 8 bits using the 256R network.
The A/D converter’s successive approximation register
(SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse. A conversion in process will be in-
terrupted by receipt of a new start conversion pulse. Con-
tinuous conversion may be accomplished by tying the
end-of-conversion (EOC) output to the SC input. If used in
this mode, an external start conversion pulse should be ap-
plied after power up. End-of-conversion will go low between
0 and 8 clock pulses after the rising edge of start conversion.
The most important section of the A/D converter is the com-
parator. It is this section which is responsible for the ultimate
accuracy of the entire converter. It is also the comparator
drift which has the greatest influence on the repeatability of
the device. A chopper-stabilized comparator provides the
most effective method of satisfying all the converter require-
ments.
The chopper-stabilized comparator converts the DC input
signal into an AC signal. This signal is then fed through a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since the
drift is a DC component which is not passed by the AC am-
plifier. This makes the entire A/D converter extremely insen-
sitive to temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the ADC0808 as
measured using the procedures outlined in AN-179.
5 www.national.com

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ADC0808CJ arduino
Applications Information (Continued)
DS005672-26
FIGURE 12. Typical Reference and Supply Circuit
DS005672-27
RA=RB
*Ratiometric transducers
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
The transition between adjacent codes N and N+1 is given
by:
The output code N for an arbitrary input are the integers
within the range:
The center of an output code N is given by:
(4)
(2) Where: VIN=Voltage at comparator input
VREF(+)=Voltage at Ref(+)
VREF(−)=Voltage at Ref(−)
VTUE=Total unadjusted error voltage (typically
VREF(+)÷512)
(3)
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