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Número de pieza ADC08062
Descripción 500 ns A/D Converter with S/H Function and Input Multiplexer
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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June 1999
ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input
Multiplexer
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a
two-channel multiplexer. The ADC08061/2 family performs
an 8-bit conversion using a 2-bit voltage estimator that gen-
erates the 2 MSBs and two low-resolution (3-bit) flashes that
generate the 6 LSBs.
Input track-and-hold circuitry eliminates the need for an ex-
ternal sample-and-hold. The ADC08061/2 family performs
accurate conversions of full-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
without need of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows the parts to be I/O or memory
mapped.
Key Specifications
n Resolution
n Conversion Time
n Full Power Bandwidth
n Throughput rate
n Power Dissipation
n Total Unadjusted Error
8 bits
560 ns max (WR-RD Mode)
300 kHz
1.5 MHz
100 mW max
±12 LSB and ±1 LSB
Features
n 1 or 2 input channels
n No external clock required
n Analog input voltage range from GND to V+
n Overflow output available for cascading (ADC08061)
n ADC08061 pin-compatible with the industry standard
ADC0820
Applications
n Mobile telecommunications
n Hard disk drives
n Instrumentation
n High-speed data acquisition systems
Block Diagram
* ADC08061
** ADC08062
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011086
DS011086-1
www.national.com

1 page




ADC08062 pdf
AC Electrical Characteristics (Continued)
The following specifications
face limits apply for TA =
apply for V+
TJ = TMIN to
= 5V, tr =
TMAX; all
tf = 10 ns,
other limits
VTRAE=F+T=J
=5V2,5V˚CR.EF−
=
0V
unless
otherwise
specified.
Bold-
Symbol
Parameter
Condition
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
tRDW
tCONV
tCRD
tACCO
RD Width
WR -RD Mode Conversion Time
(tWR + tRD + tACC1)
RD Mode Conversion Time
Access Time (Delay from Falling
Edge of RD to Output Valid)
Mode Pin to GND; (Figure 5)
Mode Pin to V+; (Figure 2)
Mode Pin to GND; (Figure 1)
CL 100 pF
Mode Pin to GND; (Figure 1)
200
400
500
655
640
250 ns (min)
400 ns (max)
560 ns (max)
900 ns (max)
900 ns (max)
tACC1
Access Time (Delay from
Falling Edge
of RD to Output Valid)
CL 10 pF
CL = 100 pF
Mode Pin to V+, tRD tINTL
(Figure 2)
45
50
110 ns (max)
tACC2
t0H
Access Time (Delay from
Falling Edge
of RD to Output Valid)
TRI-STATE® Control (Delay from
Rising Edge of RD to HI-Z State)
CL 10 pF
CL = 100 pF
tRD > tINTL; (Figures 3, 4)
RL = 3 k, CL = 10 pF
25
30
30
55 ns (max)
60 ns (max)
t1H TRI-STATE Control (Delay from
RL = 3 k, CL = 10 pF
30
60 ns (max)
Rising Edge of RD to HI-Z State)
tINTL
tINTH
Delay from Rising Edge of
WR to Falling Edge of INT
Delay from Rising Edge of
RD to Rising Edge of INT
(Figures 3, 4)
Mode Pin = V+, CL = 50 pF
CL = 50 pF; (Figures 1, 2, 3, 4)
2b, and 4 )
520
50
690 ns (max)
95 ns (max)
tINTH
Delay from Rising Edge of
CL = 50 pF; (Figure 4)
45
95 ns (max)
WR to Rising Edge of INT
tRDY Delay from CS to RDY
tID Delay from INT to Output Valid
tRI Delay from RD to INT
Mode Pin = 0V, CL = 50 pF,
RL = 3 k(Figure 1)
RL = 3 k, CL = 100 pF;
(Figure 4)
Mode Pin = V+, tRD tINTL;
(Figure 3)
25
0
60
45 ns (max)
15 ns (max)
115 ns (max)
tN Time between End of RD
and Start of New Conversion
(Figures 1, 2, 3, 4, 5)
50 50 ns (min)
tAH
tAS
tCSS
tCSH
CVIN
COUT
CIN
Channel Address Hold Time
Channel Address Setup Time
CS Setup Time
CS Hold Time
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
10 60 ns (min)
0 0 ns (max)
0 0 ns (max)
0 0 ns (min)
25 pF
5 pF
5 pF
DC Electrical Characteristics
The following specifications apply
all other limits TA = TJ = 25˚C.
for
V+
=
5V
unless
otherwise
specified.
Boldface
limits
apply
for
TA
=
TJ
=
TMIN
to
TMAX;
Symbol
Parameter
Conditions
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
VIH
Logic “1” Input Voltage
V+ = 5.5V
Mode Pin
3.5 V (min)
ADC08062
CS, WR, RD, A0 Pins
2.2 V (min)
ADC08061
CS, WR, RD Pins
2.0 V (min)
5 www.national.com

5 Page





ADC08062 arduino
Application Information (Continued)
have a voltage drop of 1/256 of the total reference voltage
(VREF+ − VREF−) across them. The remaining resistors make
up the MSB Ladder. They are made up of eight groups of
four resistors connected in series. Each MSB Ladder section
has 18 of the total reference voltage across it. Within a given
MSB Ladder section, each of the MSB resistors has 8/256,
or 1/32 of the total reference voltage across it. Tap points are
found between all of the resistors in both the MSB and LSB
Ladders. Through the Comparator Multiplexer these tap
points can be connected, in groups of eight, to the eight com-
parators shown at the right of Figure 6. This function pro-
vides the necessary reference voltages to the comparators
during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 6 form the Volt-
age Estimator. The estimator DAC connected between
VREF+ and VREF− generates the reference voltages for the
six Voltage Estimator comparators. These comparators per-
form a very low resolution A/D conversion to obtain an “esti-
mate” of the input voltage. This estimate is then used to con-
trol the Comparator Multiplexer, connecting the appropriate
MSB Ladder section to the eight flash comparators. Only 14
comparators, six in the Voltage Estimator and eight in the
flash converter, are needed to achieve the full eight-bit reso-
lution, instead of 32 comparators that would be needed by
traditional half-flash methods.
FIGURE 6. Block Diagram of the ADC08061/2 Multi-Step Flash Architecture
DS011086-18
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the es-
timator DAC. The estimator decoder then selects one of the
groups of tap points along the MSB Ladder. These eight tap
points are then connected to the eight flash comparators.
For example, if the analog input signal applied to VIN is be-
tween 0 and 3/16 of VREF (VREF = VREF+ − VREF−), the esti-
mator decoder instructs the comparator multiplexer to select
the eight tap points between 8/256 and 2/8 of VREF and con-
nects them to the eight flash comparators. The first flash
conversion is now performed, producing the five MSBs of
data.
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion. As determined by the results of the MSB flash, a
voltage from the MSB Ladder equivalent to the magnitude of
11 www.national.com

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