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PDF ADC0805LCN Data sheet ( Hoja de datos )

Número de pieza ADC0805LCN
Descripción 8-Bit uP Compatible A/D Converters
Fabricantes National Semiconductor 
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No Preview Available ! ADC0805LCN Hoja de datos, Descripción, Manual

November 1999
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit µP Compatible A/D Converters
General Description
The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation A/D
converters that use a differential potentiometric
ladder — similar to the 256R products. These converters are
designed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE® output latches di-
rectly driving the data bus. These A/Ds appear like memory
locations or I/O ports to the microprocessor and no interfac-
ing logic is needed.
Differential analog voltage inputs allow increasing the
common-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Features
n Compatible with 8080 µP derivatives — no interfacing
logic needed - access time - 135 ns
n Easy interface to all microprocessors, or operates “stand
alone”
n Differential analog voltage inputs
n Logic inputs and outputs meet both MOS and TTL
voltage level specifications
n Works with 2.5V (LM336) voltage reference
n On-chip clock generator
n 0V to 5V analog input voltage range with single 5V
supply
n No zero adjust required
n 0.3" standard width 20-pin DIP package
n 20-pin molded chip carrier or small outline package
n Operates ratiometrically or with 5 VDC, 2.5 VDC, or
analog span adjusted voltage reference
Key Specifications
n Resolution
n Total error
n Conversion time
8 bits
±14 LSB, ±12 LSB and ±1 LSB
100 µs
Connection Diagram
ADC080X
Dual-In-Line and Small Outline (SO) Packages
Ordering Information
TEMP RANGE
±14 Bit Adjusted
ERROR
±12 Bit Unadjusted
±12 Bit Adjusted
±1Bit Unadjusted
PACKAGE OUTLINE
DS005671-30
See Ordering Information
0˚C TO 70˚C
ADC0802LCWM
ADC0804LCWM
M20B — Small
Outline
0˚C TO 70˚C
−40˚C TO +85˚C
ADC0801LCN
ADC0802LCN
ADC0803LCN
ADC0804LCN
ADC0805LCN/ADC0804LCJ
N20A — Molded DIP
TRI-STATE® is a registered trademark of National Semiconductor Corp.
Z-80® is a registered trademark of Zilog Corp.
© 1999 National Semiconductor Corporation DS005671
www.national.com

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ADC0805LCN pdf
AC Electrical Characteristics (Continued)
Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).
Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7.
Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and
ADC0805, and in the ADC0804LCJ, each resistor is typically 16 k. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 k.
Note 10: Human body model, 100 pF discharged through a 1.5 kresistor.
Typical Performance Characteristics
Logic Input Threshold Voltage
vs. Supply Voltage
Delay From Falling Edge of
RD to Output Data Valid
vs. Load Capacitance
CLK IN Schmitt Trip Levels
vs. Supply Voltage
DS005671-38
fCLK vs. Clock Capacitor
Full-Scale Error vs
Conversion Time
DS005671-39
DS005671-40
Effect of Unadjusted Offset Error
vs. VREF/2 Voltage
Output Current vs
Temperature
DS005671-41
DS005671-42
Power Supply Current
vs Temperature (Note 9)
DS005671-43
Linearity Error at Low
VREF/2 Voltages
DS005671-44
DS005671-45
5
DS005671-46
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ADC0805LCN arduino
Typical Applications (Continued)
Self-Clocking in Free-Running Mode
µP Interface for Free-Running A/D
DS005671-65
*After power-up, a momentary grounding of the WR input is needed to
guarantee operation.
Operating with “Automotive” Ratiometric Transducers
DS005671-66
Ratiometric with VREF/2 Forced
*VIN(−)=0.15 VCC
15% of VCCVXDR85% of VCC
DS005671-67
DS005671-68
µP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis)
*See Figure 5 to select R value
DB7=“1” for VIN(+)>VIN(−)+(VREF/2)
Omit circuitry within the dotted area if
hysteresis is not needed
11
DS005671-69
www.national.com

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