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PDF ADC0803 Data sheet ( Hoja de datos )
| Número de pieza | ADC0803 | |
| Descripción | 8-Bit/ Microprocessor-Compatible/ A/D Converters | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
ADC0803, ADC0804
August 2002
FN3094.4
8-Bit, Microprocessor-Compatible, A/D
Converters
The ADC080X family are CMOS 8-Bit, successive-
approximation A/D converters which use a modified
potentiometric ladder and are designed to operate with the
8080A control bus via three-state outputs. These converters
appear to the processor as memory locations or I/O ports,
and hence no interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Typical Application Schematic
ANY
µPROCESSOR
1 CS
2 RD
V+ 20 +5V 150pF
CLK R 19
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
6
7
8
DIFF
INPUTS
VREF/2 9 VREF/2
DGND 10
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
Features
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . <100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• Analog Voltage Input Range
(Single + 5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0V to 5V
• No Zero-Adjust Required
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
Pinout
ADC0803, ADC0804
(PDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
Ordering Information
PART NUMBER
ADC0803LCN
ADC0804LCN
ERROR
±1/2 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
0 to 70
20 Ld PDIP
PKG. NO
E20.3
E20.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
ADC0803, ADC0804
Timing Waveforms (Continued)
V+ V+
10K
RD DATA
CS OUTPUT
CL
2.4V
RD
0.8V
DATA
OUTPUTS
V+
VOI
tr = 20ns
tr
90%
50%
10%
t0H
10%
FIGURE 1C. t0H
FIGURE 1D. t0H, CL = 10pF
FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS
Typical Performance Curves
1.8
-55oC TO 125oC
1.7
1.6
1.5
1.4
1.3
4.50
4.75 5.00 5.25
V+ SUPPLY VOLTAGE (V)
5.50
FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY
VOLTAGE
500
400
300
200
100
0
200 400 600 800
LOAD CAPACITANCE (pF)
1000
FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT
DATA VALID vs LOAD CAPACITANCE
3.5
3.1 VT(+)
2.7
-55oC TO 125oC
2.3
1.9
VT(-)
1.5
4.50
4.75
5.00
5.25
V+ SUPPLY VOLTAGE (V)
5.50
FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY
VOLTAGE
1000
R = 50K
R = 10K
R = 20K
100
10
100
CLOCK CAPACITOR (pF)
FIGURE 5. fCLK vs CLOCK CAPACITOR
1000
5
5 Page 
ADC0803, ADC0804
function. IC voltage regulators may be used for references if
the ambient temperature changes are not excessive.
Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, VlN(MlN), is not ground, a
zero offset can be done. The converter can be made to output
0000 0000 digital code for this minimum input voltage by
biasing the A/D VIN(-) input at this VlN(MlN) value (see
Applications section). This utilizes the differential mode
operation of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the VIN(-) input and applying a small magnitude
positive voltage to the VIN(+) input. Zero error is the difference
between the actual DC input voltage which is necessary to
just cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for
VREF/2 = 2.500V).
Full Scale Adjust
The full scale adjustment can be made by applying a
differential input voltage which is 11/2 LSB down from the
desired analog full scale voltage range and then adjusting
the magnitude of the VREF/2 input (pin 9) for a digital output
code which is just changing from 1111 1110 to 1111 1111.
When offsetting the zero and using a span-adjusted VREF/2
voltage, the full scale adjustment is made by inputting VMlN
to the VIN(-) input of the A/D and applying a voltage to the
VIN(+) input which is given by:
VIN(+)fSADJ = VMAX – 1.5 (---V----M-----A----X2----5-–--6--V-----M----I--N-----) ,
where:
VMAX = the high end of the analog input range, and
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)
Clocking Option
The clock for the A/D can be derived from an external source
such as the CPU clock or an external RC network can be
added to provIde self-clocking. The CLK IN (pin 4) makes
use of a Schmitt trigger as shown in Figure 16.
CLK R
R
CLK IN
C
19 ADC0803-
ADC0804
fCLK
≅
1
1.1 RC
R ≅ 10kΩ
4 CLK
FIGURE 16. SELF-CLOCKING THE A/D
Heavy capacitive or DC loading of the CLK R pin should be
avoided as this will disturb normal converter operation.
Loads less than 50pF, such as driving up to 7 A/D converter
clock inputs from a single CLK R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize the
loading on the CLK R pin (do not use a standard TTL buffer).
Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new
conversion is started. The output data latch is not updated if
the conversion in progress is not completed. The data from
the previous conversion remain in this latch.
Continuous Conversions
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a power-
up cycle to insure circuit operation. See Figure 17 for details.
150pF
N.O.
START
ANALOG
INPUTS
10K
ADC0803 - ADC0804
1 CS
V+ 20
2 RD CLK R 19
3 WR
4 CLK IN
5 INTR
6 VIN (+)
7 VIN (-)
8 AGND
9 VREF/2
10 DGND
DB0 18
DB1 17
DB2 16
DB3 15
DB4 14
DB5 13
DB6 12
DB7 11
5V (VREF)
+
10µF
LSB
DATA
OUTPUTS
MSB
FIGURE 17. FREE-RUNNING CONNECTION
Driving the Data Bus
This CMOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuItry, which is tied to the data
bus, will add to the total capacitive loading, even in three-
state (high-impedance mode). Back plane busing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logic levels on the bus and
therefore higher capacitive loads can be driven (see Typical
Performance Curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock-extending circuits (6800).
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADC0803.PDF ] | |
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