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PDF ADC-318A Data sheet ( Hoja de datos )

Número de pieza ADC-318A
Descripción 8-Bit/ 120MHz and 140MHz Full-Flash A/D Converter
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! ADC-318A Hoja de datos, Descripción, Manual

®®
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz
Full-Flash A/D Converter
FEATURES
Low power dissipation (960mW max.)
TTL compatible output
Diff./Integral nonlinearity (±½LSB max.)
1:2 Demultiplexed straight output programmable
2:1 Frequency divided TTL clock output with reset
Surface mount package
Selectable Input Logic (TTl, ECL, PECL)
+5V or ±5V Power Supply Operation
GENERAL DESCRIPTION
The ADC-318 and ADC-318A are 8 bit monolithic bipolar,
full flash A/D converters. Though they have high, 120MHz
(ADC-318) and 140MHz (ADC-318A), sampling rates, their
input logic level, including the start convert pulse, is TTL,
ECL and PECL compatible. Digital outputs are also TTL
compatible and allow a straight output or a programmable
1:2 de-multiplexed output.
The ADC-318 and ADC-318A feature ±1/2 LSB max.
integral and differential non-linearity, +5V single or ±5V dual
power supply operation, a low 960mW maximum power
dissipation, 150MHz wide analog input range and excellent
temperature coefficient in a small 48 pin QFP package. The
start convert pulse can have a 50% duty cycle.
The ADC-318 and ADC-318A offer low cost, easy to use
functionality for design engineers.
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION
PIN FUNCTION
1 –DVs (Digital)
48
2 REF. BOTTOM (VRB)
47
3 ANALOG GROUND
46
4 REF. MID POINT (VRM1) 45
5 +AVS (Analog)
44
6 ANALOG IN (VIN)
43
7 REF. MID POINT (VRM2) 42
8 +AVS (Analog)
41
9 REF. MID POINT (VRM3) 40
10 ANALOG GROUND
39
11 REF. TOP (VRT)
38
12 DIGITAL GROUND 3
37
13 A/D CLOCK ECL/PECL 36
14 A/D CLOCK ECL/PECL 35
15 A/D CLOCK TTL
34
16 NO CONNECTION
33
17 NO CONNECTION
32
18 NO CONNECTION
31
19 +DVS2 (Digital)
30
20 DIGITAL GROUND 2
29
21 B BIT 8 (LSB)
28
22 B BIT 7
27
23 B BIT 6
26
24 B BIT 5
25
RSET ECL/PECL
RSET ECL/PECL
RSET TTL
SELECT
INV
TTL CLOCK OUT
+DVS2 (Digital)
DIGITAL GROUND 2
A BIT 1 (MSB)
A BIT 2
A BIT 3
A BIT 4
A BIT 5
A BIT 6
A BIT 7
A BIT 8 (LSB)
DIGITAL GROUND 2
+DVS2 (Digital)
+DVS1 (Digital)
DIGITAL GROUND 1
B BIT 1 (MSB)
B BIT 2
B BIT 3
B BIT 4
VIN 6
VRT 11
VRM3 9
VRM2 7
VRM1 4
VRB 2
A/D CLOCK ECL/PECL 13
A/D CLOCK ECL/PECL 14
A/D CLOCK TTL 15
RSET ECL/PECL 48
RSET ECL/PECL 47
RSET TTL 46
6
6
256
6
6
DELAY
DQ
Q
8
A
LATCH
8
A
TTL
OUTPUT
44 INV
33 BIT 8 (LSB)
34 BIT 7
35 BIT 6
36 BIT 5 A OUTPUT
37 BIT 4
38 BIT 3
39 BIT 2
40 BIT 1 (MSB)
B
LATCH
6
B
TTL
OUTPUT
21 BIT 8 (LSB)
22 BIT 7
23 BIT 6
24 BIT 5 B OUTPUT
25 BIT 4
26 BIT 3
27 BIT 2
28 BIT 1 (MSB)
SELECT
43 CLOCK OUT
TTL
45 SELECT
Figure 1. ADC-318/318A Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA) Tel: (508) 339-3000, (800)233-2765 Fax: (508) 339-6356 Email: [email protected] Internet: www.datel.com

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ADC-318A pdf
®®
ADC-318, ADC-318A
ANALOG SIGNAL AIN
3ns min. 6ns max
N-1
Tds
TN
TPW1
N+2
N+1 N+3
N+4
N+5 N+6
N+7
A/D CLOCK
A DATA OUTPUT
B DATA OUTPUT
TPW0
CLOCK OUT
Trh
RSET
0ns min.
Trs
3.5ns min.
RESET PERIOD
Trh Trs
Td clock
4.5ns min. 8ns max.
2.0V
0.8V
Tdo2
6.5ns min. 10ns max.
N+1
2.0V
0.8V
N+3
N
2.0V
0.8V
Tdo1
T+2ns max.
2.0V
0.8V
N+2
~T ~T
318 318A
TPW1, min 3.2ns 3.0ns
TPW0, min 3.2ns 3.0ns
Figure 3-1: Demultiplexed Data Output (Select-Pin: +DVS or left open, 120MHz max. Clock Frequency)
ANALOG SIGNAL AIN
A/D CLOCK
A DATA OUTPUT
B DATA OUTPUT
CLOCK OUT
(inverted A/D CLOCK OUT)
RSET
N-1
T
TPW1 TPW0
Tds 3ns min. 6ns max.
N
N+1
N+2
N+3
N-4
2.0V
0.8V
N-3
N-2
N-5
2.0V
0.8V
Tdo2
N-4
6.5ns min. 10ns max.
N-3
2.0V
0.8V
Td clock
4.5ns min. 8ns max.
N-1
N-2
N
N-1
318 318A
TPW1, min 3.2ns 3.0ns
TPW0, min 3.2ns 3.0ns
Figure 3-2: Straight Data Output (Select-Pin: DGND, 100MHz max. Clock Frequency)
A/D CLOCK
CLOCK OUT 1
DATA OUT 1
(A,B)
CLOCK OUT 2
DATA OUT 2
(A,B)
A/D CLOCK
A/D CLOCK
ADC-318/318A
RSET
CLOCK OUT 1
(1) 8 DATA 1 (A, B)
8
A/D CLOCK
ADC-318/318A
RAS/DETCLOCK
CLOCK OUT 2
(2) 8 DATA 2 (A, B)
8
Figure 3-3: Parallel Operation without RSET Pulse
A/D CLOCK
RSET
CLOCK OUT 1
DATA OUT 1
(A,B)
CLOCK OUT 2
DATA OUT 2
(A,B)
A/D CLOCK
A/D CLOCK
ADC-318/318A
RSET
CLOCK OUT 1
(1) 8 DATA 1 (A, B)
8
RSET
A/D CLOCK
ADC-318/318A
RAS/EDTCLOCK
CLOCK OUT 2
(2) 8 DATA 2 (A, B)
8
Figure 3-4: Parallel Operation using RSET Synchronization
5

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