|
|
PDF CT1820 Data sheet ( Hoja de datos )
| Número de pieza | CT1820 | |
| Descripción | CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CT1820 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
CT1820
Data Terminal Bit Processor
for MIL-STD-1553 A & B
Features
• Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to
MIL-STD-1553 specifications, including Address, Mode Code and Broadcast Decoding and
Terminal Fail Safe
• Flexibility - all control lines accessible
• Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems
• Dual rank l/O registers for versatile subsystem tlmlng
• Operates from +5VDC @ 40mA typical (25mA CT1820)
• Self-contained oscillator and clock driver
• Look-ahead serial receive data output
• Self-test, on-line wraparound, plus off-line capability
1
General Description
FLEX LA
ISO
9001
CE R T I F I E D
The CT1555-3/CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the interface between a
MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal parallel data bus. The unit can be
employed as the mux bus interface for Remote Subsystems or Master Terminal Bus Controllers, thus providing a common
interface for all systems communicating over the bus.
The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status and Data
words from the bus to parallel output lines, together with error information, bus status and handshaking signals. It also
contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal Fail Safe Signal and Self Test.
In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words, under
subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation between the unit
and the subsystem for direct data flow.
The hybrid is completely compatible with all the electrical and functional spec requirements of MIL-STD-1553 A & B.
FIRST
RANK
REC’V
REG
DO - D7
FIRST
RANK
REC’V
REG
D8 - D15
SECOND
RANK
REC’V
REG
DO - D7
SECOND
RANK
REC’V
REG
D8 - D15
FIRST
RANK
XMT
REG
DO - D7
FIRST
RANK
XMT
REG
D8 - D15
SECOND
RANK
XMT
REG
DO - D7
SECOND
RANK
XMT
REG
D8 - D15
Vcc
+5V
GND
GND
1
11
34
CASE
20
36
32
{5 BIT
ADDRESS
12
8
9
10
13
SERIAL DATA OUT
RT ENABLE
(MSB) A4
A3
A2
A1
ADDRESS
DECODE
(LSB) A0
BROADCAST BROAD-
39 CAST
DECODE
MODE CODE MODE
40 CODE
DECODE
VALID WORD
14
COMM/DATA SYNC
16
DEC RST
33
TAKE DATA
37
DSC OUT
31
MANCHESTER
DECODER
&
CONTROL LOGIC
MANCHESTER
ENCODER
&
CONTROL LOGIC
OSC
&
CLOCK
DRIVER
Figure 1 – Functional Diagram
BUILT IN
TEST
SELECT
DATA IN
DATA IN
BIT SELECT
DATA OUT
DATA OUT
FAIL SAFE
TIMER
&
CONTROL
FAIL SAFE
SEND DATA
ESCOUT
SYNC SEL
ENC ENA
OUTPUT INH
MRST
+5V OSC / CLOCK POWER
XTAL
CLOCK OUT
CLOCK IN
21
22
19
25
26
15
27
28
24
23
35
38
30
29
18
17
eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT1820 REV D 6/25/99
1 page  
TRANSMIT CYCLE OPERATION
ENCODER SHIFT CLOCK (ESC) (see Figure 3)
operates at the data rate (1MHz). A low at
ENCODER ENABLE (ENC ENA) during a falling
edge of ESC x starts the Transmit cycle, which
lasts for twenty ESC clock periods. The SYNC
SELECT (SYNC SEL) input is valid at the next
low-to-high transition of ESC y. A high at SYNC
SEL will produce a data sync, or a low will produce
a command sync for that word.
Parallel data must be stable at the second rank
transmit register before SEND DATA goes high z.
Since ENC ENA is not synchronous with ESC, the
minimum time to z is 3µsec from ENC ENA leading
edge.
The first-rank transmit register may be operated
transparently (LATCH DATA always high), or may be
used to hold data ready for transmission,
independent of the activity on the 16-line subsystem
l/O bus. As long as LATCH DATA is held high, data
present on the subsystem l/O bus appears at the
output of the first rank transmit register. Stable data
may be latched and held at the first rank register
output by bringing LATCH DATA low. Data to be
transmitted may be latched any time before the
low-to high transition of SEND DATA (SEND DATA,
when appled to the LOAD DATA inputs, locks out
the data inputs to the second rank transmit
register.) For multiple word transmissions, the next
word may be inputted and latched any time after z,
but before the next low to-high transition of SEND
DATA.
SEND DATA remains high for 16 ESC periods,
during which the parallel transmit data is clocked to
the MANCHESTER ENCODER z to {. After the
sync and Manchester coded data are transmitted
through the DATA OUT and DATA OUT outputs, the
ENCODER adds on the parity bit for that word |.
If the transmitted word is to be the last word of the
transmission, ENC ENA must go high by | to
prevent initiation of another transmit cycle.
At any time, a low applied to OUTPUT INHIBIT will
force both DATA OUT and DATA OUT to a low state
without affecting any other operations.
The entire transmit cycle may be interrupted and
cleared by applying a minimum of 1µsec negative
pulse to the MASTER RESET (MRST) input.
For 8-BlT I/O subsystems, D0 is tied to D8, D1 to
D9, etc., through D7 tied to D15, and data is
inputted in 8-BlT bytes by using LATCH DATA 1 and
LATCH DATA 2 and / or LOAD DATA 1 and LOAD
DATA 2 independently.
For serial data applications, D15 input serves as the
serial transmit input. With LOAD DATA 1 held low
and LATCH DATA 1 held high, D15 input is applied
to the ENCODERís serial data input. Inputted data
must be at the ESC rate with the MSB starting at
the low-to-high transition of SEND DATA.
If a message length ever exceeds 768µsec, the
768µsec TIME OUT (FAIL SAFE) flag goes high,
and DATA OUT and DATA OUT are both forced to a
low state. This condition will remain until a valid
command word (containing the terminalís address)
is received or until MRST goes low.
ESC
012345
16 17 18 19 0 1 2 3 4 5
16 17 18 19
ENC ENA
SYNC SEL
DATA SELECT
LATCH DATA
SEND DATA
& LOAD DATA
DATA OUT
DON’T CARE
VALID
DON’T CARE
DON’T CARE
SEE
TEXT
DEPENDS ON "LATCH" TIMING
OPTIONAL NEXT-WORD LATCH
VALID
DON’T CARE
DON’T CARE
SEE
TEXT
DEPENDS ON "LATCH" TIMING
OPTIONAL NEXT-WORD LATCH
½ SYNC ½ SYNC 15 14 13
2 1 0 P ½ SYNC ½ SYNC 15 14 13
210P
DATA OUT
½ SYNC ½ SYNC 15 14 13
2 1 0 P ½ SYNC ½ SYNC 15 14 13
210P
IF USED
12
Aeroflex Circuit Technology
3 45
Figure 3 – Transmit Cycle Timing
5 SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CT1820.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CT1820 | CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B | Aeroflex Circuit Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |