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PDF A6273KA Data sheet ( Hoja de datos )
| Número de pieza | A6273KA | |
| Descripción | 8-BIT LATCHED DMOS POWER DRIVER | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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6273
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
CLEAR 1
IN 1 2
IN 2 3
OUT 1 4
OUT2 5
OUT 3 6
OUT4 7
IN 3 8
IN 4 9
GROUND 10
VDD 20
LOGIC
SUPPLY
19 IN 8
18 IN 7
17 OUT8
16 OUT7
15 OUT6
14 OUT 5
13 IN 6
12 IN 5
11 STROBE
Dwg. PP-015-2
Note that the A6273KA (DIP) and the A6273KLW
(SOIC) are electrically identical and share a com-
mon terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................. 50 V
Output Drain Current,
Continuous, IO ....................... 250 mA*
Peak, IOM .............................. 750 mA*†
Peak, IOM ..................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS .............................................. 75 mJ
Logic Supply Voltage, VDD ................ 7.0 V
Input Voltage Range,
VI ................................. -0.3 V to +7.0 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range,
TA .............................. -40°C to +125°C
Storage Temperature Range,
TS .............................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input
static protection (Class 3) but are still
susceptible to damage if exposed to extremely
high static electrical charges.
8-BIT LATCHED
DMOS POWER DRIVER
The A6273KA and A6273KLW combine eight (positive-edge-
triggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microproces-
sor-based systems. Use with TTL may require appropriate pull-up
resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6273KA/KLW DMOS open-drain outputs are
capable of sinking up to 750 mA. Similar devices with reduced rDS(on)
will be available as the A6A273.
The A6273KA is furnished in a 20-pin dual in-line plastic package.
The A6273KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applica-
tions. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85°C.
FEATURES
I 50 V Minimum Output Clamp Voltage
I 250 mA Output Current (all outputs simultaneously)
I 1.3 Ω Typical rDS(on)
I Low Power Consumption
I Replacements for TPIC6273N and TPIC6273DW
Always order by complete part number:
Part Number
A6273KA
A6273KLW
Package
20-pin DIP
20-lead SOIC
RθJA
55°C/W
70°C/W
RθJC
25°C/W
17°C/W
1 page  
6273
8-BIT LATCHED
DMOS POWER DRIVER
TIMING REQUIREMENTS
INx
STROBE
OUTPUTx
50%
t su(D) t h(D)
50%
t PLH
10%
tr
50%
t su(D) t h(D)
t PHL
90%
tf
Dwg. WP-036-1
Input Active Time Before Strobe
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Input Active Time After Strobe
(Data Hold Time), th(D) ................................................... 20 ns
Input Pulse Width, tw(D) ...................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VDD
Input Logic Low, VIL ................................................. ≤ 0.15VDD
www.allegromicro.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet A6273KA.PDF ] | |
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