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PDF A29800TM-90 Data sheet ( Hoja de datos )

Número de pieza A29800TM-90
Descripción 1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only/ Boot Sector Flash Memory
Fabricantes AMIC Technology 
Logotipo AMIC Technology Logotipo



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No Preview Available ! A29800TM-90 Hoja de datos, Descripción, Manual

A29800 Series
Preliminary
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
n 5.0V ± 10% for read and write operations
n Access times:
- 55/70/90 (max.)
n Current:
- 28mA read current (word mode)
- 20 mA typical active read current (byte mode)
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
n Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
n Top or bottom boot block configurations available
n Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125°C
- Reliable operation for the life of the system
n Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
n Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
n Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
n Hardware reset pin (RESET )
- Hardware method to reset the device to reading array
data
n Package options
- 44-pin SOP or 48-pin TSOP (I)
General Description
The A29800 is a 5.0 volt only Flash memory organized as
1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The
A29800 offers the RESET function. The 1024 Kbytes of data
are further divided into nineteen sectors for flexible sector erase
capability. The 8 bits of data appear on I/O0 - I/O7 while the
addresses are input on A1 to A18; the 16 bits of data appear on
I/O0~I/O15. The A29800 is offered in 44-pin SOP and 48-Pin
TSOP packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply. Additional
12.0 volt VPP is not required for in-system write or erase
operations. However, the A29800 can also be programmed in
standard EPROM programmers.
The A29800 has the first toggle bit, I/O6, which indicates whether
an Embedded Program or Erase is in progress, or it is in the
Erase Suspend. Besides the I/O6 toggle bit, the A29800 has a
second toggle bit, I/O2, to indicate whether the addressed sector
is being selected for erase. The A29800 also offers the ability to
program in the Erase Suspend mode. The standard A29800
offers access times of 55, 70 and 90 ns, allowing high-speed
microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable ( CE ), write
enable ( WE ) and output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29800 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the
device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command
sequence. This initiates the Embedded Erase algorithm - an
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase
operation.
PRELIMINARY (May, 2001, Version 0.0)
1
AMIC Technology, Inc.

1 page




A29800TM-90 pdf
A29800 Series
Word/Byte Configuration
The BYTE pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE pin
is set at logic ”1”, the device is in word configuration, I/O15-
I/O0 are active and controlled by CE and OE .
If the BYTE pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled
by CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is
used as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH all
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to
the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing
waveforms, lCC1 in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE and CE
to VIL, and OE to VIH. An erase operation can erase one
sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each sector
occupies. A "sector address" consists of the address inputs
required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
OE input.
The device enters the CMOS standby mode when the CE
& RESET pins are both held at VCC ± 0.5V. (Note that this
is a more restricted voltage range than VIH.) The device
enters the TTL standby mode when CE is held at VIH,
while RESET is held at VCC±0.5V. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
The RESET pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
PRELIMINARY (May, 2001, Version 0.0)
5
AMIC Technology, Inc.

5 Page





A29800TM-90 arduino
A29800 Series
START
Embedded
Program
algorithm in
progress
Increment Address
Write Program
Command
Sequence
Data Poll
from System
Verify Data ?
Yes
No
Last Address ?
Yes
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched.
Figure 3 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50µs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50µs, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50µs, the system need not monitor I/O3. Any
command other than Sector Erase or Erase Suspend during
the time-out period resets the device to reading array data.
The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the
final WE pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are
ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of the
erase operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
PRELIMINARY (May, 2001, Version 0.0)
11
AMIC Technology, Inc.

11 Page







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