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PDF ACS406CS Data sheet ( Hoja de datos )
| Número de pieza | ACS406CS | |
| Descripción | Acapella Optical Modem IC | |
| Fabricantes | Semtech Corporation | |
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Acapella Optical Modem IC
ACS406CS Main Features
* Full duplex serial transmission through a single fiber-optic
cable without the need for expensive WDM devices.
* E2 data-rates of 8.448Mbps or 4 * E1 at 2.048Mbps.
T2 data rates of 6.312Mbps or 4 * T1 at 1.544Mbps.
* 4 clock domains for independent transmission of 4 * E1 or
4 * T1 data channels.
* Link lengths up to 25km (50km at reduced bandwidth).
* Single wavelength of light to transmit and receive data.
* Low power, zero cross talk between Rx and Tx channels.
* Incorporates up to 4 maintenance channel at 16kbps
or 1 channel at 64kbps.
* Bit Error Rate (BER) of < 10-10
* Typical latency of 0.75ms.
Single fiber full duplex system using ACS406CS chip set
with a quad T1/E1 Framer IC.
General Description
The ACS406CS is a complete controller, driver and receiver chip-set,
supporting full-duplex synchronous transmission up to 8.448/6.312Mbps
over a single-optical fiber. The designer can share the available
bandwidth over 1 to 8 main channels by selecting the appropriate
combination on the DR input pins. In addition to the main channels, the
ACS406CS provides either 1 x 64kbps or 4 x 16kbps auxilliary
maintenance channels.
The internal machine cycle provides for link lengths up to 25/50km. On
the electrical side HDB3/AMI/NRZ/B8ZS interfaces are selectable.
Communicating modems automatically maintain synchronisation with
each other, such that the receive phase of one modem is lined-up with
the transmit phase of the other, compensating for the propagation delay
presented by the link. Link lengths from zero to maximum distance are
catered for automatically.
1 page  
pin should then be set high to return the device to
the operation mode. The preset Laser power will
then be maintained over the recommended
temperature and voltage range.
Receive Monitor
The ACS9010 incorporates a power meter which
generates a current source which is proportional to the
received optical current.
I*
RxMN
=6
*
I(PIN)
* Tolerance = +/- 20%.
I = Amps
IRxMN flows through a resistor, internal to the ACS9010,
connected between RxMN and GND. The internal
resistor has a value of 260KΩ +/- 20 %.
RxMN is compared with 1.25V. If RxMN exceeds
1.25V, then output RxFLG is set = 1, otherwise
RxFLG is set = 0. With the internal resistor of 260ΚΩ,
the default threshold for the RxFLG is a input current
of 800nA +/- 25%. By adding an external parallel
resistor between RxMN and GND, this threshold may
be increased.
will be referred to collectively as RCLK.
The data appearing on RPOS/RNEG is valid on the
rising or falling edge of the RCLK clock dependent
on the setting of RESEL (see Figure 1. Timing
diagrams). To ensure that the average receive
frequency is the same as the transmitted frequency,
RCLK is generated from a Digital Phase-Lock Loop
(DPLL) system (except where master mode has been
selected). The DPLL makes periodic corrections to
the output RCLK clock by subtracting or adding a
single crystal clock bit-period, so that the average
frequency of the RCLK clock tracks the average
frequency of the transmit clock of the far-end modem
(or system master clock). This decompression/de-
jittering function is covered in more detail in section
headed, Jitter Characteristics.
Data Coding
The main synchronous channels may use any of the
following coding methods; NRZ, AMI, HDB3, B8ZS.
The desired mode is selected by POL1 and POL2
input pins, as shown in Table 2.
The voltage on RxMN will modulate with receive data
bursts. It will settle to its correct value within 4us
following the start of a receive burst, and will collapse
to 0V after a burst ends.
Transmission Clock TCLK
Data Coding
AMI
HDB3
B8ZS
NRZ
POL2
0
0
1
1
POL1
0
1
0
1
Table 2
There are four independent transmit clocks on the
ACS406CS; TCLK1,TCLK2,TCLK3 and TCLK4. For
the purpose of this specification, these signals will
be referred to collectively as TCLK.
The ACS406CS gives a choice between internally
and externally generated transmit clocks. When the
CKC pin is held Low, the set of TCLK clocks are
configured as outputs producing a clock at the
frequency defined by DR(5:1).
When the CKC pin is held High, the set of TCLK
clocks are configured as inputs, and will accept an
externally produced transmission clock with a
tolerance of up to 250ppm with respect to the
transmission rate determined by DR(5:1).
The data appearing on TPOS/TNEG is valid on the
rising or falling edge of the TCLK clock dependent
on the setting of TRSEL (see Figure 1. Timing
diagrams). This is the case for both internally and
externally generated transmission clocks.
Receive Clock RCLK
There are four independent receive clocks on the
ACS406CS; RCLK1, RCLK2, RCLK3 and RCLK4.
For the purpose of this specification, these signals
For Non-Return-to-Zero (NRZ) coding, data is applied
directly to TPOS inputs, and output data appears
only on the RPOS output pins (except for 8-channel
mode, see section headed, Multi-Channel Operation).
When using NRZ code, unconnected TNEG input
pins will automatically pull-up to VD+. In addition, the
ACS406CS will assert a continuous Low on redundant
RNEG output pins.
AMI, B8ZS and HDB3 coding is normally bipolar.
However, it is possible to interface with the
ACS406CS using two inputs and outputs rather than
a single bipolar interface. Data equivalent to positive
excursions of the bipolar AMI/B8ZS/HDB3 signal are
applied as a logic High to TPOS, while data equivalent
to negative excursions are applied as a logic High to
TNEG. Similarly, AMI/B8ZS/HDB3 positive
excursions will appear as a logic High on RPOS and
negative excursions will appear as a logic High on
RNEG.
It is anticipated that most users of the ACS406CS
will interface directly with a E1/T1 framers. All the
popular framers provide POS/NEG bipolar interfaces
which will directly connect to the ACS4060.
If required, a detailed description of the AMI/HDB3
coding rules are available from Acapella.
ACS406CS Issue 1.6 January 1999.
5
5 Page 
For 1-channel operation in either TX1 or HT mode
then TmD1/RmD1 will be available for transmission
but data appearing on TmD2 will be ignored.
For 2-channel operation in TX2 mode then both
TmD1/RmD1 and TmD2/RmD2 are available for
transmission. TmD1 is associated with channel 1
and is clocked by TCLK1/RCLK1. TmD2 is associated
with channel 2 and is clocked by TCLK2/RCLK2.
For TX4 mode and all other data formats, Frame
mode is currently unavailable.
Although, the data applied to the TmD1/2 is clocked
by TCLK with the same resolution as TCLK the
number of transitions allowed on these inputs is
restricted according to the rules below.
TX1 mode
A maximum of 2 transitions are permitted on TmD1
for each 512 TCLK1 clock period. If two transitions
occur sequentially (on two successive TCLK cycles)
then this may be counted as one transition.
TX2 mode
A maximum of 2 transitions may occur on both TmD1/
2 for each 128 TCLK1/2 clock period. If two transitions
occur sequentially (on two successive TCLK1/2
cycles) then this may be counted as one transition.
HT mode
A maximum of 2 transitions may occur on TmD1 for
each 128 TCLK1 clock period. If two transitions occur
sequentially (on two successive TCLK1 cycles) then
this may be counted as one transition.
In frame mode, TPOS/TNEG and the associated
TmD data are transmitted over the link in phase and
will appear in phase at the RPOS/RNEG and RmD
outputs at the far-end ACS406CS.
A typical application of frame mode follows:
In an E1 frame, only 30 of the available 32 symbols
are available for data transmission, the remaining
two symbols are deployed for frame synchronisation
and signalling. In a proprietary system, it is possible
to use the TmD1/2 support channels to mark the
first bit or first word of each frame, thus freeing up
extra bandwidth in the main data channel.
Configuration Modes
The ACS406CS has six Configuration Modes
controlled by CM(3:1) as shown in Table 22. It can be
seen that the CM(3:1) settings also control the lock
mode (See section headed Lock Modes).
Configuration Mode Lock CM3 CM2 CM1
Full-duplex
Full-duplex
Full-duplex
Full-duplex slave
Full-duplex master
Full-duplex
Drift
Memory
Random
Active
Drift
Active
0
0
0
1
1
1
00
01
11
01
10
11
Table 22
Full-Duplex
In the full-duplex configuration, the RCLK clock of
both devices track the average frequency of the
corresponding TCLK clock of the opposite end of
the link. The receiving Digital-Phase-Lock Loop
(DPLL) system makes periodic adjustments to the
RCLK clock to ensure that the average frequency is
exactly the same as the far-end TCLK clock. In
summary, each TCLK is an independent master
clock and each RCLK a slave of the far-end TCLK
clock.
The relationship between TmCLK and RmCLK are
treated similarly.
Full-Duplex Slave
In slave mode, the TCLK and RCLK clock is derived
from the TCLK clock of the far-end modem, such
that their average frequencies are identical. Clearly,
it is essential that only one modem within a
communicating pair is configured in slave mode.
The CKC pin should be forced to GND, so that
TCLK is always configured as an output. Since only
one device in the modem pair may be configured in
slave mode, the mode also selects active lock. See
section headed, Locking Modes.
The relationship between TmCLK and RmCLK are
treated similarly. The CKM pin should be forced to
GND, so that TmCLK is always configured as an
output.
4 Support channel mode, M4B=0
The ACS406CS has provision for 1 or 4 maintenance
channel mode. This is controlled by the signal M4B.
When M4B =1, then the number of maintenance
channels is set at 1 with a 32/64kHz TmCLK clock per
channel, determined by DR(5:1). When M4B = 0, then
the number of maintenance channels is increased to 4
with a reduced 8/16kHz TmCLK clock per channel,
determined by DR(5:1). This mode is only available for
Maintenance channel mode, Frame = 0.
Full-Duplex Master
In master mode, the local RCLK clock is internally
generated from the local TCLK clock. The local
TCLK clock may be internally or externally generated.
Master mode is only valid if the far-end device is
configured in slave mode or if the far-end TCLK
clock is derived from the far-end RCLK clock. Only
one modem within a communicating pair may be
configured as a master.
ACS406CS Issue 1.6 January 1999.
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ACS406CS.PDF ] | |
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