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5 V/ Serial-Input Voltage-Output/ 14-Bit DACs - Analog Devices

Número de pieza AD5552
Descripción 5 V/ Serial-Input Voltage-Output/ 14-Bit DACs
Fabricantes Analog Devices 
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AD5552 datasheet

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AD5552 pdf
AD5551/AD5552
Mnemonic
RFB
VOUT
AGNDF
AGNDS
VREFS
VREFF
CS
SCLK
NC
DIN
LDAC
DGND
INV
VDD
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5552 PIN FUNCTION DESCRIPTIONS
Description
Feedback Resistor. In bipolar mode connect this pin to external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from
2 V to VDD.
This is the voltage reference input (force) for the DAC. Connect to external reference ranges
from 2 V to VDD.
This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
No Connect.
Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on
the rising edge of SCLK.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with
the contents of the input register.
Digital Ground. Ground reference for digital circuitry.
Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps
inverting input in bipolar mode.
Analog Supply Voltage, 5 V ± 10%.
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 1.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum
ensures monotonicity. TPC 4 illustrates a typical DNL versus
code plot.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
Zero Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition. A plot of the glitch impulse is shown
in TPC 14.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. CS is
held high, while the CLK and DIN signals are toggled. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa. A typi-
cal plot of digital feedthrough is shown in TPC 13.
Power Supply Rejection Ratio
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power-supply rejection
ratio is quoted in terms of % change in output per % change in
VDD for full-scale output of the DAC. VDD is varied by ± 10%.
Reference Feedthrough
This is a measure of the feedthrough from the VREF input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in mV p-p.
REV. 0
–5–

5 Page

AD5552 arduino
AD5551/AD5552
Force Sense Buffer Amplifier Selection
These amplifiers can be single-supply or dual supplies, low-
noise amplifiers. A low-output impedance at high frequencies
is preferred as they need to be able to handle dynamic currents
of up to ± 20 mA.
Reference and Ground
As the input impedance is code-dependent, the reference pin
should be driven from a low-impedance source. The AD5551/
AD5552 operates with a voltage reference ranging from 2 V to
VDD. Although DAC’s full-scale output voltage is determined
by the reference, references below 2 V will result in reduced
accuracy. Tables I and II outline the analog output voltage
for particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5552.
If the application does not require separate force and sense lines,
they should be tied together close to the package to minimize
voltage drops between the package leads and the internal die.
ADR291 and ADR293 are suitable references for this product.
Power-On Reset
These parts have a power-on reset function to ensure the output
is at a known state upon power-up. On power-up, the DAC
register contains all zeros, until data is loaded from the serial
register. However, the serial register is not cleared on power-up,
so its contents are undefined. When loading data initially to the
DAC, 14 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 14 bits are loaded,
only the last 14 are kept, and if fewer than 14 are loaded, bits
will remain from the previous word. If the AD5551/AD5552
needs to be interfaced with data shorter than 14 bits, the data
should be padded with zeros at the LSBs.
Power Supply and Reference Bypassing
For accurate high-resolution performance, it is recommended that
the reference and supply pins be bypassed with a 10 µF tantalum
capacitor in parallel with a 0.1 µF ceramic capacitor.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5551/AD5552 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5551/AD5552
requires a 14-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5552 only).
ADSP-2101/ADSP-2103 to AD5551/AD5552 Interface
Figure 5 shows a serial interface between the AD5551/AD5552
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set to operate in the SPORT (Serial Port) transmit
alternate framing mode. The ADSP-2101/ADSP-2103 is pro-
grammed through the SPORT control register and should be
configured as follows: Internal Clock Operation, Active Low
Framing, 16-Bit Word Length. The first 2 bits are DON’T CARE
as AD5551/AD5552 will keep the last 14 bits. Transmission is
initiated by writing a word to the Tx register after the SPORT has
been enabled. Because of the edges-triggered difference, an inverter
is required at the SCLKs between the DSP and the DAC.
FO
ADSP-2101/ TFS
ADSP-2103*
DT
SCLK
LDAC**
CS AD5551/
AD5552*
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY
Figure 5. ADSP-2101/ADSP-2103 to AD5551/AD5552
Interface
68HC11 to AD5551/AD5552 Interface
Figure 6 shows a serial interface between the AD5551/AD5552
and the 68HC11 microcontroller. SCK of the 68HC11 drives
the SCLK of the DAC, while the MOSI output drives the
serial data lines SDIN. CS signal is driven from one of the
port lines. The 68HC11 is configured for master mode; MSTR
= 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI
output is valid on the rising edge of SCK.
68HC11/
68L11*
PC6
PC7
MOSI
SCK
LDAC**
CS AD5551/
AD5552*
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY
Figure 6. 68HC11/68L11 to AD5551/AD5552 Interface
MICROWIRE to AD5551/AD5552 Interface
Figure 7 shows an interface between the AD5551/AD5552 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5551/
AD5552 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
CS
MICROWIRE*
SO
SCLK
CS
DIN AD5551/
AD5552*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 7. MICROWIRE to AD5551/AD5552 Interface
80C51/80L51 to AD5551/AD5552 Interface
A serial interface between the AD5551/AD5552 and the 80C51/
80L51 microcontroller is shown in Figure 8. TxD of the
microcontroller drives the SCLK of the AD5551/AD5552, while
RxD drives the serial data line of the DAC. P3.3 is a bit program-
mable pin on the serial port which is used to drive CS.
80C51/
80L51*
P3.4
P3.3
RxD
TxD
LDAC**
CS AD5551/
AD5552*
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5552 ONLY
Figure 8. 80C51/80L51 to AD5551/AD5552 Interface
–10–
REV. 0

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