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Número de pieza AD7887
Descripción +2.7 V to +5.25 V/ Micropower/ 2-Channel/ 125 kSPS/ 12-Bit ADC in 8-Lead uSOIC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a +2.7 V to +5.25 V, Micropower, 2-Channel,
125 kSPS, 12-Bit ADC in 8-Lead SOIC
AD7887
FEATURES
Specified for VDD of +2.7 V to +5.25 V
Flexible Power/Throughput Rate Management
Shutdown Mode: 1 A Max
One/Two Single-Ended Inputs
Serial Interface: SPI™/QSPI™/MICROWIRE™/DSP
Compatible
8-Lead Narrow SOIC and SOIC Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Instrumentation and Control Systems
High Speed Modems
FUNCTIONAL BLOCK DIAGRAM
AIN0
VREF/
AIN1
VDD
I/P
MUX
T/H
AD7887
VREF/AIN1
SOFTWARE
CONTROL
LATCH
2.5V
REF
BUF
CHARGE
REDISTRIBUTION
DAC
COMP
GND
GENERAL DESCRIPTION
The AD7887 is a high speed, low power, 12-bit ADC that oper-
ates from a single +2.7 V to +5.25 V power supply. The AD7887
is capable of 125 kSPS throughput rate. The input track-and-
hold acquires a signal in 500 ns and features a single-ended
sampling scheme. The output coding for the AD7887 is straight
binary and the part is capable of converting full power signals up to
2.5 MHz.
The AD7887 can be configured for either dual or single chan-
nel operation, via the on-chip Control Register. There is a
default single-channel mode that allows the AD7887 to be
operated as a read-only ADC. In single-channel operation,
there is one analog input (AIN0) with the VREF/AIN1 pin as-
suming its VREF function. This VREF pin allows the user access
to the part’s internal +2.5 V reference, or the VREF pin can be
overdriven by an external reference to provide the reference
voltage for the part. This external reference voltage has a range
of +2.5 V to VDD. The analog input range on AIN0 is 0 to +VREF.
In dual-channel operation, the VREF/AIN1 pin assumes its AIN1
function, providing a second analog input channel. In this case,
the reference voltage for the part is provided via the VDD pin. As
a result, the input voltage range on both the AIN0 and AIN1
inputs is 0 to VDD.
SAR + ADC
CONTROL LOGIC
SPORT
DIN CS DOUT SCLK
CMOS construction ensures low power dissipation of typically
2 mW for normal operation and 3 µW in power-down mode.
The part is available in an 8-lead, 0.15-inch-wide narrow body
SOIC and an 8-lead µSOIC package.
PRODUCT HIGHLIGHTS
1. Smallest 12-bit dual/single-channel ADC; 8-lead µSOIC
package.
2. Lowest power 12-bit dual/single-channel ADC.
3. Flexible power management options including automatic
power-down after conversion.
4. Read-Only ADC capability.
5. Analog input range from 0 V to VREF.
6. Versatile serial I/O port (SPI/QSPI/MICROWIRE/DSP
compatible).
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

1 page




AD7887 pdf
PIN CONFIGURATION
CS 1
8 SCLK
VDD 2 AD7887 7 DOUT
TOP VIEW
GND 3 (Not to Scale) 6 DIN
AIN1/VREF 4
5 AIN0
AD7887
PIN FUNCTION DESCRIPTIONS
Pin Pin
No. Mnemonic Function
1 CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7887 and also frames the serial data transfer. When the AD7887 operates in its default mode, the CS pin
also acts as the shutdown pin such that with the CS pin high, the AD7887 is in its power-down mode.
2 VDD
Power Supply Input. The VDD range for the AD7887 is from +2.7 V to +5.25 V. When the AD7887 is con-
figured for two-channel operation, this pin also provides the reference source for the part.
3 GND
Ground Pin. This pin is the ground reference point for all circuitry on the AD7887. In systems with separate
AGND and DGND planes, these planes should be tied together as close as possible to this GND pin. Where
this is not possible, this GND pin should connect to the AGND plane.
4 AIN1/VREF Analog Input 1/Voltage Reference Input. In single-channel mode, this pin becomes the reference input/
output. In this case, the user can either access the internal +2.5 V reference or overdrive the internal refer-
ence with the voltage applied to this pin. The reference voltage range for an externally-applied reference is
+1.2 V to VDD. In two-channel mode, this pin provides the second analog input channel AIN1. The input
voltage range on AIN1 is 0 to VDD.
5 AIN0
Analog Input 0. In single-channel mode, this is the analog input and the input voltage range is 0 to VREF. In
dual-channel mode, it has an analog input range of 0 to VDD.
6 DIN
Data In. Logic Input. Data to be written to the AD7887’s Control Register is provided on this input and is
clocked into the register on the rising edge of SCLK (see Control Register section). The AD7887 can be
operated as a single-channel read-only ADC by tying the DIN line permanently to GND.
7 DOUT Data Out. Logic Output. The conversion result from the AD7887 is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four
leading zeros followed by the 12 bits of conversion data, which is provided MSB first.
8 SCLK
Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing serial
data to the Control Register. This clock input is also used as the clock source for the AD7887’s conversion
process.
REV. B
–5–

5 Page





AD7887 arduino
AD7887
MODES OF OPERATION
The AD7887 has a number of different modes of operation.
These are designed to provide flexible power management op-
tions. These options can be chosen to optimize the power dissi-
pation/throughput rate ratio for differing application requirements.
The modes of operation are controlled by the PM1 and PM0 bits
of the Control Register as previously outlined. For read-only
operation of the AD7887, the default mode of all 0s in the Con-
trol Register can be set up by tying the DIN line permanently
low.
Mode 1 (PM1 = 0, PM0 = 0)
This mode allows the user to control the powering down of the
part via the CS pin. Whenever CS is low, the AD7887 is fully
powered up; whenever CS is high, the AD7887 is in full shut-
down. When CS goes from high to low, all on-chip circuitry
starts to power up. It takes approximately, 5 µs for the AD7887
internal circuitry to be fully powered up. As a result, a conver-
sion (or sample-and-hold acquisition) should not be initiated
during this 5 µs.
Figure 13 shows a general diagram of the operation of the AD7887
in this mode. The input signal is sampled on the second rising
edge of SCLK following the CS falling edge. The user should
ensure that 5 µs elapses between the falling edge of CS and the
second rising edge of SCLK. In microcontroller applications,
this is readily achievable by driving the CS input from one of the
port lines and ensuring that the serial data read (from the micro-
controllers serial port) is not initiated for 5 µs. In DSP applica-
tions, where the CS is generally derived from the serial frame
synchronization line, it is usually not possible to separate the CS
falling edge and second SCLK rising edge by up to 5 µs without
affecting the speed of the rest of the serial clock. Therefore, the
user will need to write to the Control Register to exit this mode
and (by writing PM1 = 0 and PM0 = 1) put the part into Mode
2, i.e., normal mode. A second conversion will then need to be
initiated when the part is powered-up to get a conversion result.
The write operation which takes place in conjunction with this
second conversion can put the part back into Mode 1 and the
part will go into power-down mode when CS returns high.
Mode 2 (PM1 = 0, PM0 = 1)
In this mode of operation, the AD7887 remains fully powered
up regardless of the status of the CS line. It is intended for
fastest throughput rate performance as the user does not have to
worry about the 5 µs power-up time previously mentioned.
Figure 14 shows the general diagram of the operation of the
AD7887 in this mode.
The data presented to the AD7887 on the DIN line during the
first eight clock cycles of the data transfer are loaded to the
Control Register. To continue to operate in this mode, the user
must ensure that PM1 is loaded with 0 and PM0 is loaded with
1 on every data transfer.
The falling edge of CS initiates the sequence and the input
signal is sampled on the second rising edge of the SCLK input.
Sixteen serial clock cycles are required to complete the conver-
sion and access the conversion result. Once a data transfer is
complete (CS has returned high), another conversion can be
initiated immediately by bringing CS low again.
THE PART POWERS UP ON CS
FALLING EDGE AS PM1 AND PM0 = 0
CS
SCLK
1
THE PART POWERS DOWN ON CS
RISING EDGE AS PM1 AND PM0 = 0
16
DOUT
DIN
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE
Figure 13. Mode 1 Operation
REV. B
CS
SCLK
DOUT
DIN
THE PART REMAINS POWERED UP
AT ALL TIMES AS
PM1 = 0 AND PM0 = 1
1 16
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE
Figure 14. Mode 2 Operation
–11–

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