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PDF AD7872 Data sheet ( Hoja de datos )
| Número de pieza | AD7872 | |
| Descripción | LC2MOS Complete 14-Bit/ Sampling ADCs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Complete Monolithic 14-Bit ADC
2s Complement Coding
Parallel, Byte and Serial Digital Interface
80 dB SNR at 10 kHz Input Frequency
57 ns Data Access Time
Low Power—50 mW typ
83 kSPS Throughput Rate
16-Lead SOIC (AD7872)
APPLICATIONS
Digital Signal Processing
High Speed Modems
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
LC2MOS
Complete 14-Bit, Sampling ADCs
AD7871/AD7872
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The AD7871 and AD7872 are fast, complete, 14-bit analog-to-
digital converters. They consist of a track/hold amplifier,
successive-approximation ADC, 3 V buried Zener reference and
versatile interface logic. The ADC features a self-contained, laser
trimmed internal clock, so no external clock timing components
are required. The on-chip clock may be overridden to synchronize
ADC operation to the digital system for minimum noise.
The AD7871 offers a choice of three data output formats: a sin-
gle, parallel, 14-bit word; two 8-bit bytes or a 14-bit serial data
stream. The AD7872 is a serial output device only. The two
parts are capable of interfacing to all modern microprocessors
and digital signal processors.
The AD7871 and AD7872 operate from ± 5 V power supplies,
accept bipolar input signals of ± 3 V and can convert full power
signals up to 41.5 kHz.
In addition to the traditional dc accuracy specifications, the
AD7871 and AD7872 are also fully specified for dynamic perfor-
mance parameters including distortion and signal-to-noise ratio.
Both devices are fabricated in Analog Devices’ LC2MOS mixed
technology process. The AD7871 is available in 28-pin plastic DIP
and PLCC packages. The AD7872 is available in a 16-pin plastic
DIP, hermetic DIP and 16-lead SOIC packages.
PRODUCT HIGHLIGHTS
1. Complete 14-Bit ADC on a Chip.
2. Dynamic Specifications for DSP Users.
3. Low Power.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
1 page  
AD7871/AD7872
AD7872 PIN FUNCTION DESCRIPTION
DIP
No. Mnemonic
1 CONTROL
2 CONVST
3 CLK
4 SSTRB
5 SCLK
6 SDATA
7 NC
8 DGND
9 VDD
10 NC
11 CREF
12 AGND
13 REF OUT
14 VIN
15 VSS
16 VDD
Function
Control Input. With this pin at 0 V, the SCLK is noncontinuous; with this pin at –5 V, the SCLK
is continuous.
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This
input is asynchronous to the CLK.
Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying
this pin to VSS, enables the internal laser-trimmed oscillator.
This is an active low three-state output that provides a framing pulse for serial data. An external
4.7 kΩ pull-up resistor is required on SSTRB.
Serial Clock. SCLK is the gated serial clock output derived from the internal or external ADC
clock. If the 14/8/CLK input is at –5 V, then the SCLK runs continuously. With CONTROL
at 0 V, it is gated off (three-state) after serial transmission is complete. SCLK is an open-drain
output and requires an external 2 kΩ pull-up resistor.
Serial Data. This is the three-state serial data output used in conjunction with SCLK and SSTRB in
serial data transmission. Serial data is valid on the falling edge of SCLK, when SSTRB is low. An
external 4.7 kΩ pull-up resistor is required on SDATA.
No Connect.
Digital Ground. Ground return for digital circuitry.
Positive Supply for analog circuitry, +5 V ± 5%.
No Connect.
Decoupling point for on-chip reference. Connect 10 nF capacitor between this pin and AGND.
Analog Ground. Ground reference for analog circuitry.
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load
capability is 500 µA.
Analog Input. The input range is ± 3 V.
Negative Supply, –5 V ± 5%.
Positive Supply for analog circuitry, +5 V ± 5%. Pin 16 and Pin 9 should be connected together.
PIN CONFIGURATIONS
DIP DIP, SOIC
PLCC
REV. D
–5–
5 Page 
AD7871/AD7872
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second and third or-
der terms are of different significance. The second order terms
are usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to the
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs. In this case, the
input consists of two, equal amplitude, low distortion sine waves.
Figure 16 shows a typical IMD plot for the AD7871/AD7872.
microprocessor and the conversion result is read from the ADC
with the following instruction:
ADSP-2100 MR0 = DM(ADC)
TMS32020/C25: IN D,ADC
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
ADC = AD7871 Address
Figure 17. AD7871 to ADSP-2100 Parallel Interface
Figure 16. IMD Plot
Peak Harmonic or Spurious Noise
Peak Harmonic or Spurious Noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fs/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, peak
will be a noise peak.
MICROPROCESSOR INTERFACE
The AD7871 and AD7872 have a wide variety of interfacing op-
tions. The AD7871 offers two operating modes and three
data-output formats, while the AD7872 is a dedicated serial
output device. The fast data access times on the parallel modes
of the AD7871 allow interfacing to the very fast DSPs. The se-
rial mode on both the AD7871 and AD7872 is compatible with
the serial port structures on all the popular DSPs.
Parallel Read Interfacing
Figures 17 and 18 show interfaces to the ADSP-2100 and the
TMS32020/C25 DSP processors. The AD7871 is operating in
Mode 1, parallel read for both interfaces. An external timer con-
trols conversion start asynchronously to the microprocessor. At
the end of each conversion the ADC BUSY/INT interrupts the
Figure 18. AD7871 to TMS32020/C25 Interface
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option is
to decode the AD7871 CONVST from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note, a read opera-
tion must not be attempted during conversion.
REV. D
–11–
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| PDF Descargar | [ Datasheet AD7872.PDF ] | |
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