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PDF AD7870A Data sheet ( Hoja de datos )

Número de pieza AD7870A
Descripción LC2MOS Complete/ 12-Bit/ 100 kHz / Sampling ADC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a LC2MOS
Complete, 12-Bit, 100 kHz , Sampling ADC
AD7870A
FEATURES
Complete Monolithic 12-Bit ADC with:
2 s Track/Hold Amplifier
8 s A/D Converter
On-Chip Reference
Laser-Trimmed Clock
Parallel, Byte and Serial Digital Interface
70 dB SNR at 10 kHz Input Frequency
57 ns Data Access Time
Low Power—60 mW typ
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7870A is a fast, complete, 12-bit A/D converter. It con-
sists of a track/hold amplifier, 8 µs successive approximation
ADC, 3 V buried Zener reference and versatile interface logic.
The ADC features a self-contained internal clock that is laser
trimmed to guarantee accurate control of conversion time. No
external clock timing components are required; the on-chip
clock may be overridden by an external clock if required.
AD7870A offers a choice of three data output formats: a single,
parallel, 12-bit word, two 8-bit bytes or serial data. Fast bus
access times and standard control inputs ensure easy interfacing
to modern microprocessors and digital signal processors.
The AD7870A operates from ± 5 V power supplies, accepts
bipolar input signals of ± 3 V and can convert full power signals
up to 50 kHz.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7870A is also fully
specified for dynamic performance parameters including har-
monic distortion and signal-to-noise ratio.
The AD7870A is fabricated in Analog Devices’ linear compati-
ble CMOS (LC2MOS) process, a mixed technology process that
combines precision bipolar circuits with low power CMOS logic.
The part is available in a 24-pin, 0.3-inch wide, plastic dual in-
line package (DIP).
PRODUCT HIGHLIGHTS
1. Complete 12-bit ADC on a chip.
The AD7870A is the most complete monolithic ADC avail-
able and combines a 12-bit ADC with internal clock, track/
hold amplifier and reference on a single chip.
2. Dynamic specifications for DSP users.
The AD7870A is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and inter-
modulation distortion. Key digital timing parameters are also
tested and guaranteed over the full operating temperature
range.
3. Fast microprocessor interface.
Data access times of 57 ns make the AD7870A compatible
with modern 8- and 16-bit microprocessors and digital signal
processors.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997

1 page




AD7870A pdf
AD7870A
Pin Pin
No. Mnemonic
1 RD
2 INT
3 CLK
4 DB11/HBEN
5 DB10/SSTRB
6 DB9/SCLK
7 DB8/SDATA
8–11 DB7/LOW–
DB4/LOW
12 DGND
13-16 DB3/DB11–
DB0/DB8
17 VDD
18 AGND
19 REF OUT
20 VIN
21 VSS
22 12/8/CLK
23 CONVST
24 CS
PIN DESCRIPTION
Function
Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.
Interrupt, Active low logic output indicating converter status. See timing diagrams.
Clock input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying
this pin to VSS enables the internal laser-trimmed clock oscillator.
Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the
12/8/CLK input (see below). When 12-bit parallel data is selected, this pin provides the DB11 output.
When byte data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus
interfacing. When HBEN is low, DB7/LOW to DB0/DB8 become DB7 to DB0. With HBEN high,
DB7/LOW to DB0/DB8 are used for the upper byte of data (see Table I).
Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output.
SSTRB is an active low open-drain output that provides a strobe or framing pulse for serial data. An
external 4.7 kpull-up resistor is required on SSTRB.
Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is
the gated serial clock output derived from the internal or external ADC clock. If the 12/8/CLK input is at
–5 V, then SCLK runs continuously. If 12/8/CLK is at 0 V, then SCLK is gated off after serial
transmission is complete. SCLK is an open-drain output and requires an external 2 kpull-up resistor.
Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA
is an open-drain serial data output which is used with SCLK and SSTRB for serial data transfer. Serial
data is valid on the falling edge of SCLK while SSTRB is low. An external 4.7 kpull-up resistor is
required on SDATA.
Three-state data outputs controlled by CS and RD. Their function depends on the 12/8/CLK
and HBEN inputs. With 12/8/CLK high, they are always DB7–DB4. With 12/8/CLK low or –5 V, their
function is controlled by HBEN (see Table I).
Digital Ground. Ground reference for digital circuitry.
Three-state data outputs which are controlled by CS and RD. Their function depends on the 12/8/CLK
and HBEN inputs. With/12/8/CLK high, they are always DB3–DB0. With 12/8/CLK low or –5 V, their
function is controlled by HBEN (see Table I).
Positive Supply, +5 V ± 5%.
Analog Ground. Ground reference for track/hold, reference and DAC.
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability
is 500 µA.
Analog Input. The analog input range is ± 3 V.
Negative Supply, –5 V ± 5%.
Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the
output data format is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK
is not continuous. With this pin at –5 V, either byte or serial data is again available but SCLK is now
continuous.
Convert Start. A high to low transition on this input puts the track/hold into its hold mode and starts
conversion. This input is asynchronous to the CLK and independent of CS and RD.
Chip Select. Active low logic input. The device is selected when this input is active.
HBEN
HIGH
LOW
Table I. Output Data for Byte Interfacing
DB7/LOW
LOW
DB7
DB6/LOW
LOW
DB6
DB5/LOW
LOW
DB5
DB4/LOW
LOW
DB4
DB3/DB11 DB2/DB10
DB11 (MSB) DB10
DB3 DB2
DB1/DB9
DB9
DB1
DB0/DB8
DB8
DB0 (LSB)
REV. 0
–5–

5 Page





AD7870A arduino
AD7870A
V(i) the estimated code transition point is derived as follows:
V
(i
)
=
A
×
Cos
π
×
cum(i
N
)
where A is the peak signal amplitude,
N is the number of histogram samples
and cum(i) = in = 0 V(n) occurrences
Figure 14. AC INL Plot
APPLICATION HINTS
Good printed circuit board (PCB) layout is as important as the
overall circuit design itself in achieving high speed A/D perfor-
mance. The AD7870A is required to make bit decisions on an
LSB size of 1.465 mV. Thus, the designer has to be conscious of
noise both in the ADC itself and in the preceding analog circuitry.
Switching mode power supplies are not recommended as the
switching spikes will feed through to the comparator causing
noisy code transitions. Other causes of concern are ground loops
and digital feedthrough from microprocessors. These are factors
that influence any ADC, and a proper PCB layout that mini-
mizes these effects is essential for best performance.
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the digi-
tal and analog signal lines separated as much as possible. Take
care not to run any digital track alongside an analog signal track.
Guard (screen) the analog input with AGND.
Establish a single point analog ground (star ground) separate
from the logic system ground at the AD7870A AGND pin or as
close as possible to the AD7870A. Connect all other grounds
and the AD7870A DGND to this single analog ground point.
Do not connect any other digital grounds to this analog ground
point.
Low impedance analog and digital power supply common re-
turns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. The use of
ground planes minimizes impedance paths and also guards the
analog circuitry from digital noise.
NOISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable be-
tween the source and the ADC. Reduce the ground circuit im-
pedance as much as possible since any potential difference in
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic DIP (N-24)
REV. 0
–11–

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