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PDF AD7866 Data sheet ( Hoja de datos )

Número de pieza AD7866
Descripción Dual 1 MSPS/ 12-Bit/ 2-Channel SAR ADC with Serial Interface
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
FEATURES
Dual 12-Bit, 2-Channel ADC
Fast Throughput Rate
1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low Power
11.4 mW Max at 1 MSPS with 3 V Supplies
24 mW Max at 1 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB SNR at 300 kHz Input Frequency
Onboard Reference 2.5 V
Flexible Power/Throughput Rate Management
Simultaneous Conversion/Read
No Pipeline Delays
High-Speed Serial Interface SPITM/QSPITM/
MICROWIRETM/DSP Compatible
Shut-Down Mode
1 A Max
20-Lead TSSOP Package
Dual 1 MSPS, 12-Bit, 2-Channel
SAR ADC with Serial Interface
AD7866
FUNCTIONAL BLOCK DIAGRAM
VREF
DCAPA REF SELECT AVDD DVDD
2.5V
REF
VA1
VA2 MUX
BUF
12-BIT
T/H SUCCESSIVE-
APPROXIMATION
ADC
AD7866
OUTPUT
DRIVERS
CONTROL
LOGIC
VB1
VB2 MUX
T/H
BUF
12-BIT
SUCCESSIVE-
APPROXIMATION
ADC
OUTPUT
DRIVERS
DOUTA
A0
RANGE
SCLK
CS
VDRIVE
DOUTB
AGND AGND
DCAPB
DGND
GENERAL DESCRIPTION
The AD7866 is a dual 12-bit high-speed, low power, successive-
approximation ADC. The part operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a low-noise, wide
bandwidth track/hold amplifier which can handle input frequencies
in excess of 10 MHz.
The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS and conversion is also initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipelined delays associated with the part.
The AD7866 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 3 V supplies
and 1 MSPS throughput rate, the part consumes a maximum of
3.8 mA. With 5 V supplies and 1 MSPS, the current consumption
is a maximum of 4.8 mA. The part also offers flexible power/
throughput rate management when operating in sleep mode.
The analog input range for the part can be selected to be a 0 V
to VREF range or a 2 × VREF range with either straight binary or
two’s complement output coding. The AD7866 has an
on-chip 2.5 V reference which can be overdriven if an external
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
reference is preferred. Each on-board ADC can also be supplied
with a separate individual external reference.
The AD7866 is available in a 20-lead thin shrink small outline
(TSSOP) package.
PRODUCT HIGHLIGHTS
1. The AD7866 features two complete ADC functions allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input multiplexer. The conversion
result of both channels is available simultaneously on separate
data lines, or both may be taken on one data line if only one
serial port is available.
2. High Throughput with Low Power Consumption—The
AD7866 offers a 1 MSPS throughput rate with 11.4 mW
maximum power consumption when operating at 3 V.
3. Flexible Power/Throughput Rate Management—The
conversion rate is determined by the serial clock allowing
the power consumption to be reduced as the conversion time
is reduced through a SCLK frequency increase. Power
efficiency can be maximized at lower throughput rates if the
part enters sleep during conversions.
4. No Pipeline Delay—The part features two standard successive-
approximation ADCs with accurate control of the sampling
instant via a CS input and once off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

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AD7866 pdf
AD7866
ORDERING GUIDE
Model
Temperature Range
Resolution
(Bits)
Package Description
Package
Option
AD7866ARU
–40°C to +85°C
AD7866BRU
–40°C to +85°C
EVAL-AD7866CB1
Evaluation Board
EVAL-CONTROL BRD22 Controller Board
12
12
Thin Shrink SO (TSSOP)
Thin Shrink SO (TSSOP)
(TSSOP)
RU-20
RU-20
NOTES
1This can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.
2This evaluation board controller is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATION
REF SELECT 1
20 A0
DCAPB 2
AGND 3
19 CS
18 SCLK
VB2 4
17 VDRIVE
VB1 5 AD7866 16 DOUTB
VA2
6 TOP VIEW 15
(Not to Scale)
DOUTA
VA1 7
14 DGND
AGND 8
DCAPA 9
VREF 10
13 DVDD
12 AVDD
11 RANGE
Pin No. Mnemonic
1 REF SELECT
2, 9 DCAPB, DCAPA
3, 8 AGND
4, 5 VB2, VB1
6, 7 VA2, VA1
10 VREF
PIN FUNCTION DESCRIPTIONS
Function
Internal/External Reference Selection Pin. Logic Input. If this pin is tied to GND, the on-chip
2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, pins VREF,
DCAPA, and DCAPB must be tied to decoupling capacitors. If the REF SELECT pin is tied to a
logic high, an external reference can be supplied to the AD7866 through the VREF pin, in which
case decoupling capacitors are required on DCAPA and DCAPB. However, if the VREF pin is tied to
AGND while REF SELECT is tied to a logic low, an individual external reference can be applied
to both ADC A and ADC B through pins DCAPA and DCAPB, respectively. See Reference section.
Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective
ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a
system. Depending on the polarity of the REF SELECT pin and the configuration of the VREF pin,
these pins can also be used to input a separate external reference to each ADC. The range of the
external reference is dependent on the analog input range selected. See Reference section.
Analog Ground. Ground reference point for all analog circuitry on the AD7866. All analog input
signals and any external reference signal should be referred to this AGND voltage. Both of these
pins should connect to the AGND plane of a system. The AGND and DGND voltages should
ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.
Analog Inputs of ADC B. Single-ended analog input channels. The input range on each channel is 0 V
to VREF or a 2 × VREF range depending on the polarity of the RANGE pin upon the falling edge of CS.
Analog Inputs of ADC A. Single-ended analog input channels. The input range on each channel is 0 V
to VREF or a 2 × VREF range depending on the polarity of the RANGE pin upon the falling edge of CS.
Reference Decoupling Pin and External Reference Selection Pin. This pin is connected to the inter-
nal reference and requires a decoupling capacitor. The nominal reference voltage is 2.5 V and this
appears at the pin; however, if the internal reference is to be used externally in a system, it must be
taken from either the DCAPA or DCAPB pins. This pin is also used in conjunction with the REF SELECT
pin when applying an external reference to the AD7866. See REF SELECT pin description.
REV. 0
–5–

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AD7866 arduino
AD7866
analog input range will be 0 V to VREF and the output coding
from the part will be straight binary (for the next conversion). If this
pin is at a logic high when CS goes low, then the analog input
range will be 2 × VREF and the output coding for the part will
be two’s complement. However, if after the falling edge of CS,
the logic level of the RANGE pin has changed upon the eighth
falling SCLK edge, point B, the output coding will change to the
other option without any change in the analog input range. So for
the next conversion, two’s complement output coding could be selected
with a 0 V to VREF input range, for example, if the RANGE pin
is low upon the falling edge of CS and high upon the eighth falling
SCLK edge, as shown in Figure 7. Figures 5 through 8 show
examples of timing diagrams when selecting a particular analog input
range with a particular output coding format. Table I also summarizes
the required logic level of the RANGE pin for each selection.
The Logic Input A0 is used to select the pair of channels to be
converted simultaneously. The Logic state of this pin is also
checked upon the falling edge of CS and the multiplexers are set
up for the next conversion. If it is low, the following conversion
will be performed on Channel 1 of each ADC; if it is high,
the following conversion will be performed on Channel 2 of
each ADC.
Handling Bipolar Input Signals
Figure 9 shows how useful the combination of the 2 × VREF input
range and the two’s complement output coding scheme is for
handling bipolar input signals. If the bipolar input signal is biased
about VREF and two’s complement output coding is selected,
then VREF becomes the zero code point, –VREF is negative full-
scale and +VREF becomes positive full-scale, with a dynamic
range of 2 × VREF.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/4096.
The ideal transfer characteristic for the AD7866 when straight
binary coding is selected is shown in Figure 10 and the ideal
transfer characteristic for the AD7866 when two’s complement
coding is selected is shown in Figure 11.
Table I. Analog Input and Output Coding Selection
Range Level
@ Point A1
Range Level
@ Point B2
Low
High
Low
High
Low
High
High
Low
NOTES
1Point A = Falling edge of CS.
2Point B = Eighth falling edge of SCLK.
3Selected for NEXT conversion.
Input Range3
0 V to VREF
VREF ± VREF
VREF /2 ± VREF /2
0 V to 2 × VREF
Output Coding3
Straight Binary
Two’s Complement
Two’s Complement
Straight Binary
CS
SCLK
RANGE
A
1
B
8
0V TO VREF
INPUT RANGE
16 1
16
DOUTA
DOUTB
STRAIGHT BINARY
Figure 5. Selecting 0 V to VREF Input Range with Straight Binary Output Coding
REV. 0
CS
SCLK
RANGE
A
1
B
8
VREF ؎ VREF
INPUT RANGE
16 1
16
DOUTA
DOUTB
TWOS COMPLEMENT
Figure 6. Selecting VREF ± VREF Input Range with Two’s Complement Output Coding
–11–

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