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PDF AD7859 Data sheet ( Hoja de datos )
| Número de pieza | AD7859 | |
| Descripción | 3 V to 5 V Single Supply/ 200 kSPS 8-Channel/ 12-Bit Sampling ADCs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
3 V to 5 V Single Supply, 200 kSPS
8-Channel, 12-Bit Sampling ADCs
AD7859/AD7859L*
FEATURES
Specified for VDD of 3 V to 5.5 V
AD7859–200 kSPS; AD7859L–100 kSPS
System and Self-Calibration
Low Power
Normal Operation
AD7859: 15 mW (VDD = 3 V)
AD7859L: 5.5 mW (VDD = 3 V)
Using Automatic Power-Down After Conversion (25 W)
AD7859: 1.3 mW (VDD = 3 V 10 kSPS)
AD7859L: 650 W (VDD = 3 V 10 kSPS)
Flexible Parallel Interface:
16-Bit Parallel/8-Bit Parallel
44-Pin PQFP and PLCC Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTION
The AD7859/AD7859L are high speed, low power, 8-channel,
12-bit ADCs which operate from a single 3 V or 5 V power
supply, the AD7859 being optimized for speed and the
AD7859L for low power. The ADC contains self-calibration
and system calibration options to ensure accurate operation over
time and temperature and have a number of power-down
options for low power applications.
The AD7859 is capable of 200 kHz throughput rate while the
AD7859L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7859 and AD7859L input
voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2
about VREF/2 (bipolar) with both straight binary and 2s comple-
ment output coding respectively. Input signal range is to the
supply and the part is capable of converting full-power signals to
100 kHz.
CMOS construction ensures low power dissipation of typically
5.4 mW for normal operation and 3.6 µW in power-down mode.
The part is available in 44-pin, plastic quad flatpack package
(PQFP) and plastic lead chip carrier (PLCC).
AIN1
AIN8
REFIN/
REFOUT
CREF1
CREF2
CAL
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AD7859/AD7859L
I/P
MUX
T/H
2.5V
REFERENCE
BUF
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION MEMORY
AND
CONTROLLER
SAR + ADC
CONTROL
PARALLEL INTERFACE/CONTROL REGISTER
DB15 – DB0
RD CS WR W/B
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. Flexible power management options including automatic
power-down after conversion.
3. By using the power management options a superior power
performance at slower throughput rates can be achieved.
AD7859: 1 mW typ @ 10 kSPS
AD7859L: 1 mW typ @ 20 kSPS
4. Operates with reference voltages from 1.2 V to the supply.
5. Analog input ranges from 0 V to VDD.
6. Self and system calibration.
7. Versatile parallel I/O port.
8. Lower power version AD7859L.
*Patent pending.
See page 28 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
1.6mA
IOL
TO OUTPUT
PIN
50pF
200µA
IOH
+2.1V
Figure 1. Load Circuit for Digital Output Timing
Specifications
Model
ORDERING GUIDE
Linearity
Error
(LSB)1
Power
Dissipation Package
(mW)
Option2
AD7859AP
±1
AD7859AS
±1
AD7859BS
± 1/2
AD7859LAS3
±1
EVAL-AD7859CB4
EVAL-CONTROL BOARD5
15
15
15
5.5
P-44A
S-44
S-44
S-44
NOTES
1Linearity error refers to the integral linearity error.
2P = PLCC; S = PQFP.
3L signifies the low power version.
4This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5This board is a complete unit allowing a PC to control and communicate with
all Analog Devices, Inc. evaluation boards ending in the CB designators.
For more information on Analog Devices products and evaluation boards, visit
our World Wide Web home page at http://www.analog.com.
PINOUT FOR PLCC
AD7859/AD7859L
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1500 kV
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latchup.
PINOUT FOR PQFP
6 5 4 3 2 1 44 43 42 41 40
NC 7
W/B 8
REFIN/REFOUT 9
AVDD 10
AGND 11
CREF1 12
CREF2 13
AIN0 14
AIN1 15
AIN2 16
AIN3 17
AD7859
TOP VIEW
(Not to Scale)
39 NC
38 DB11
37 DB10
36 DB9
35 DB8/HBEN
34 DGND
33 DVDD
32 DB7
31 DB6
30 DB5
29 DB4
18 19 20 21 22 23 24 25 26 27 28
NC 1
W/B 2
REFIN/REFOUT
AVDD
3
4
AGND 5
CREF1
CREF2
6
7
AIN0 8
AIN1 9
AIN2 10
AIN3 11
PIN NO. 1 IDENTIFIER
AD7859
TOP VIEW
(Not to Scale)
33 NC
32 DB11
31 DB10
30 DB9
29 DB8/HBEN
28 DGND
27 DVDD
26 DB7
25 DB6
24 DB5
23 DB4
REV. A
–5–
5 Page 
AD7859/AD7859L
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
MSB
ZERO
READ STATUS REGISTER
Figure 4. Flowchart for Reading the Status Register
ZERO SGL/DIFF CHSLT2 CHSLT1 CHSLT0 PMGT1 PMGT0
ONE
ONE
AMODE
BUSY
CALMD CALSLT1 CALSLT0
STCAL
LSB
Bit Mnemonic
15 ZERO
14 ZERO
13 SGL/DIFF
12 CHSLT2
11 CHSLT1
10 CHSLT0
9 PMGT1
8 PMGT0
7 ONE
6 ONE
5 AMODE
4 BUSY
3 CALMD
2 CALSLT1
1 CALSLT0
0 STCAL
STATUS REGISTER BIT FUNCTION DESCRIPTION
Comment
These two bits are always 0.
Single/Differential Bit.
Channel Selection Bits. These bits, in conjunction with the SGL/DIFF bit, determine which channel has
been selected for conversion. Please refer to Table IIIa and Table IIIb.
Power Management Bits. These bits along with the SLEEP pin indicate if the part is in a power-down
mode or not. See Table VI in Power-Down Section for description.
Both these bits are always 1.
Analog Mode Bit. This bit is used along with SGL/DIFF and CHSLT2 – CHSLT0 to determine the
AIN(+) and AIN(–) inputs to the track and hold circuitry and the analog conversion mode (unipolar or bi-
polar). Please see Table III for details.
Conversion/Calibration BUSY Bit. When this bit is a 1, there is a conversion or a calibration in progress.
When this bit is a zero, there is no conversion or calibration in progress.
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a
system calibration is selected (see Table IV).
Calibration Selection Bits. The CALSLT1 and CALSLT0 bits indicate which of the calibration
registers are addressed for reading and writing (see section on the Calibration Registers for more details).
Start Calibration Bit. The STCAL bit is a 1 if a calibration is in progress and a 0 if there is no calibration in
progress.
REV. A
–11–
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7859.PDF ] | |
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