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PDF AD7858L Data sheet ( Hoja de datos )

Número de pieza AD7858L
Descripción 3 V to 5 V Single Supply/ 200 kSPS 8-Channel/ 12-Bit Sampling ADC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
3 V to 5 V Single Supply, 200 kSPS
8-Channel, 12-Bit Sampling ADC
FEATURES
Specified for VDD of 3 V to 5.5 V
AD7858—200 kSPS; AD7858L—100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power
AD7858: 12 mW (VDD = 3 V)
AD7858L: 4.5 mW (VDD = 3 V)
Automatic Power-Down After Conversion (25 W)
Flexible Serial Interface:
8051/SPI™/QSPI™/P Compatible
24-Lead DIP, SOIC, and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High-Speed Modems
GENERAL DESCRIPTION
The AD7858/AD7858L are high-speed, low-power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7858 being optimized for speed and the AD7858L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en-
sure accurate operation over time and temperature and have a
number of power-down options for low-power applications.
The part powers up with a set of default conditions and can
operate as a read-only ADC.
The AD7858 is capable of 200 kHz throughput rate while the
AD7858L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a
pseudo-differential sampling scheme. The AD7858/AD7858L
voltage range is 0 to VREF with straight binary output coding.
Input signal range is to the supply and the part is capable of con-
verting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
4.5 mW for normal operation and 1.15 mW in power-down
mode with a throughput rate of 10 kSPS (VDD = 3 V). The part
is available in 24-lead, 0.3 inch-wide dual-in-line package
(DIP), 24-lead small outline (SOIC), and 24-lead small shrink
outline (SSOP) packages.
AD7858/AD7858L*
FUNCTIONAL BLOCK DIAGRAM
AIN1
AIN8
REFIN/REFOUT
CREF1
CREF2
CAL
AVDD
AGND
I/P
MUX
T/H
2.5V
REFERENCE
BUF
AD7858/
AD7858L
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY AND
CONTROLLER
SAR AND ADC
CONTROL
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
SERIAL INTERFACE/CONTROL REGISTER
SYNC
DIN
DOUT SCLK
PRODUCT HIGHLIGHTS
1. Specified for 3 V and 5 V supplies.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
4. Operates with reference voltages from 1.2 V to VDD.
5. Analog input range from 0 V to VDD.
6. Eight single-ended or four pseudo-differential input channels.
7. System and self-calibration.
8. Versatile serial I/O port (SPI/QSPI/8051/µP).
9. Lower power version AD7858L.
*Patent pending.
See page 31 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 page




AD7858L pdf
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 100 kHz (AD7858L) or
200 kHz (AD7858), reading and writing must be performed
during conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSY
to the next rising edge of CONVST) before the next conversion
begins to ensure that the part is settled to the 12-bit level. If the
user does not want to provide the CONVST signal, the conver-
sion can be initiated in software by writing to the control register.
AD7858/AD7858L
1.6mA IOL
TO
OUTPUT
PIN
CL
100pF
200A IOH
+2.1V
Figure 1. Load Circuit for Digital Output Timing
Specifications
CONVST (I/P)
t2
BUSY (O/P)
tCONVERT = 4.6s MAX, 10s MAX FOR L VERSION
t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V
t1
tCONVERT
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
t3
t4
THREE-STATE
1
t6
DB15
t7
DB15
t8
t9
56
t6 t10
DB11
t11
16
t12
DB0
THREE-
STATE
DB11
DB0
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
CONVST (I/P)
t2
BUSY (O/P)
t1
tCONVERT = 4.6s MAX, 10s MAX FOR L VERSION
t1 = 100ns MIN, t4 = 50/90ns MAX 5V/3V, t7 = 40/60ns MIN 5V/3V
tCONVERT
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
t3
1
t4
THREE-STATE
t6
DB15
t7
DB15
t8
t9
56
t6 t10
DB11
t11
16
t12
DB0
THREE-
STATE
DB11
DB0
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
REV. B
–5–

5 Page





AD7858L arduino
CALMD
0
0
0
0
1
1
1
1
AD7858/AD7858L
Table III. Channel Selection
SGL/DIFF
CH2
CH1
CH0
AIN(+)*
AIN(–)*
0
00
0 AIN1
0
00
1 AIN3
0
01
0 AIN5
0
01
1 AIN7
0
10
0 AIN2
0
10
1 AIN4
0
11
0 AIN6
0
11
1 AIN8
1
00
0 AIN1
1
00
1 AIN3
1
01
0 AIN5
1
01
1 AIN7
1
10
0 AIN2
1
10
1 AIN4
1
11
0 AIN6
1
11
1 AIN8
*AIN(+) refers to the positive input seen by the AD7858/AD7858L sample and hold circuit,
*AIN() refers to the negative input seen by the AD7858/AD7858L sample and hold circuit.
AIN2
AIN4
AIN6
AIN8
AIN1
AIN3
AIN5
AIN7
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
CALSLT1
0
0
1
1
0
0
1
1
CALSLT0
0
1
0
1
0
1
0
1
Table IV. Calibration Selection
Calibration Type
A Full Internal Calibration is initiated where the Internal DAC is calibrated
followed by the Internal Gain Error, and finally the Internal Offset Error is
calibrated out. This is the default setting.
Here the Internal Gain Error is calibrated out followed by the Internal Offset
Error calibrated out.
This calibrates out the Internal Offset Error only.
This calibrates out the Internal Gain Error only.
A Full System Calibration is initiated here where first the Internal DAC is
calibrated followed by the System Gain Error, and finally the System Offset
Error is calibrated out.
Here the System Gain Error is calibrated out followed by the System Offset
Error.
This calibrates out the System Offset Error only.
This calibrates out the System Gain Error only.
REV. B
–11–

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