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PDF AD7856 Data sheet ( Hoja de datos )

Número de pieza AD7856
Descripción 5 V Single Supply/ 8-Channel 14-Bit 285 kSPS Sampling ADC
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
5 V Single Supply, 8-Channel
14-Bit 285 kSPS Sampling ADC
AD7856
FEATURES
Single 5␣ V Supply
285 kSPS Throughput Rate
Self- and System Calibration with Autocalibration on
Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power: 60 mW Typ
Automatic Power-Down After Conversion (2.5␣ W Typ)
Flexible Serial Interface: 8051/SPI™/QSPI™/P Compatible
24-Lead DIP, SOIC and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AIN1
AIN8
REFIN/REFOUT
CREF1
CREF2
CAL
I/P
MUX
T/H
4.096V
REFERENCE
BUF
AD7856
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY AND
CONTROLLER
SAR + ADC
CONTROL
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
GENERAL DESCRIPTION
The AD7856 is a high speed, low power, 14-bit ADC that oper-
ates from a single 5 V power supply. The ADC powers up with
a set of default conditions at which time it can be operated as a
read only ADC. The ADC contains self-calibration and system
calibration options to ensure accurate operation over time and
temperature and it has a number of power-down options for low
power applications.
The AD7856 is capable of 285 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7856 voltage range is 0 to
VREF with straight binary output coding. Input signal range is to
the supply and the part is capable of converting full power sig-
nals to 10 MHz.
CMOS construction ensures low power dissipation of typically
60 mW for normal operation and 5.1 mW in power-down mode
at 10 kSPS throughput rate. The part is available in 24-lead,
0.3 inch-wide dual in-line package (DIP), 24-lead small outline
(SOIC) and 24-lead small shrink outline (SSOP) packages.
Please see page 31 for data sheet index.
SERIAL INTERFACE/CONTROL REGISTER
SYNC
DIN
DOUT
SCLK
PRODUCT HIGHLIGHTS
1. Single 5 V supply.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
4. Operates with reference voltages from 1.2 V to VDD.
5. Analog input range from 0 V to VDD.
6. Eight single-ended or four pseudo-differential input channels.
7. Self- and system calibration.
8. Versatile serial I/O port (SPI/QSPI/8051/µP).
SPI and QSPI are trademarks of Motorola, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998

1 page




AD7856 pdf
AD7856
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 285 kHz, reading and writ-
ing must be performed during conversion as in Figure 3. At
least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
1.6mA IOL
TO OUTPUT
PIN CL
100pF
+2.1V
200A IOL
Figure 1. Load Circuit for Digital Output Timing
Specifications
CONVST (I/P)
t2
BUSY (O/P)
tCONVERT = 3.5s MAX, 5.25s MAX FOR K VERSION
t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K
t1
tCONVERT
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
t3
t4
THREE-STATE
1
t6
DB15
t7 t8
DB15
t9
56
t10
t6
DB11
t11
16
t12 THREE-
DB0
STATE
DB11
DB0
Figure 2. Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
CONVST (I/P)
t2
BUSY (O/P)
t1
tCONVERT = 3.5s MAX, 5.25s MAX FOR K VERSION
t1 = 100ns MIN, t4 = 30/50ns MAX A/K, t7 = 30/40ns MIN A/K
tCONVERT
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
t3
t4
THREE-STATE
1
t6
DB15
t7 t8
DB15
t9
56
t10
t6
DB11
t11
16
t12
THREE-
DB0
STATE
DB11
DB0
Figure 3. Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
REV. A
–5–

5 Page





AD7856 arduino
CALMD
0
0
0
0
1
1
1
1
AD7856
Table III. Channel Selection
SGL/DIFF
CH2
CH1
CH0
0 000
0 001
0 010
0 011
0 100
0 101
0 110
0 111
1 000
1 001
1 010
1 011
1 100
1 101
1 110
1 111
*AIN(+) refers to the positive input seen by the AD7856 sample and hold circuit.
AIN(–) refers to the negative input seen by the AD7856 sample and hold circuit.
AIN(+)*
AIN1
AIN3
AIN5
AIN7
AIN2
AIN4
AIN6
AIN8
AIN1
AIN3
AIN5
AIN7
AIN2
AIN4
AIN6
AIN8
AIN(–)*
AIN2
AIN4
AIN6
AIN8
AIN1
AIN3
AIN5
AIN7
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
CALSLT1
0
0
1
1
0
0
1
1
Table IV. Calibration Selection
CALSLT0
0
1
0
1
0
1
0
1
Calibration Type
A Full Internal Calibration is initiated where the Internal DAC is calibrated
followed by the Internal Gain Error, and finally the Internal Offset Error is
calibrated out. This is the default setting.
Here the Internal Gain Error is calibrated out followed by the Internal Offset
Error calibrated out.
This calibrates out the Internal Offset Error only.
This calibrates out the Internal Gain Error only.
A Full System Calibration is initiated here where first the Internal DAC is
calibrated followed by the System Gain Error, and finally the System Offset
Error is calibrated out.
Here the System Gain Error is calibrated out followed by the System Offset
Error.
This calibrates out the System Offset Error only.
This calibrates out the System Gain Error only.
REV. A
–11–

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