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PDF AD7854 Data sheet ( Hoja de datos )

Número de pieza AD7854
Descripción 3 V to 5 V Single Supply/ 200 kSPS 12-Bit Sampling ADCs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
3 V to 5 V Single Supply, 200 kSPS
12-Bit Sampling ADCs
FEATURES
Specified for VDD of 3 V to 5.5 V
Read-Only Operation
AD7854–200 kSPS; AD7854L–100 kSPS
System and Self-Calibration
Low Power
Normal Operation
AD7854: 15 mW (VDD = 3 V)
AD7854L: 5.5 mW (VDD = 3 V)
Automatic Power-Down After Conversion (25 W)
AD7854: 1.3 mW 10 kSPS
AD7854L: 650 W 10 kSPS
Flexible Parallel Interface
12-Bit Parallel/8-Bit Parallel (AD7854)
28-Lead DIP, SOIC and SSOP Packages (AD7854)
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
AIN(+)
AIN(–)
REFIN/
REFOUT
CREF1
CREF2
AD7854/AD7854L*
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AD7854/AD7854L
T/H
2.5V
REFERENCE
BUF
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
DVDD
DGND
CLKIN
CONVST
BUSY
PARALLEL INTERFACE/CONTROL REGISTER
DB11–DB0
CS RD WR HBEN
GENERAL DESCRIPTION
The AD7854/AD7854L is a high speed, low power, 12-bit ADC
that operates from a single 3 V or 5 V power supply, the
AD7854 being optimized for speed and the AD7854L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en-
sure accurate operation over time and temperature and has a
number of power-down options for low power applications.
The AD7854 is capable of 200 kHz throughput rate while the
AD7854L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7854 and AD7854L input
voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2,
centered at VREF/2 (bipolar). The coding is straight binary in
unipolar mode and twos complement in bipolar mode. Input
signal range is to the supply and the part is capable of convert-
ing full-power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
5.4 mW for normal operation and 3.6 µW in power-down mode.
The part is available in 28-lead, 0.6 inch wide dual-in-line pack-
age (DIP), 28-lead small outline (SOIC) and 28-lead small
shrink outline (SSOP) packages.
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. Flexible power management options including automatic
power-down after conversion. By using the power manage-
ment options a superior power performance at slower
throughput rates can be achieved:
AD7854: 1 mW typ @ 10 kSPS
AD7854L: 1 mW typ @ 20 kSPS
3. Operates with reference voltages from 1.2 V to AVDD.
4. Analog input ranges from 0 V to AVDD.
5. Self-calibration and system calibration.
6. Versatile parallel I/O port.
7. Lower power version AD7854L.
*Patent pending.
See Page 27 for data sheet index.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 page




AD7854 pdf
1.6mA IOL
TO
OUTPUT
PIN
CL
50pF
200µA IOH
+2.1V
Figure 1. Load Circuit for Digital Output Timing
Specifications
PIN CONFIGURATION
FOR DIP, SOIC AND SSOP
CONVST 1
28 BUSY
WR 2
27 CLKIN
RD 3
26 DB11
CS 4
25 DB10
REFIN/REFOUT 5 AD7854 24 DB9
AVDD 6 TOP VIEW 23 DGND
AGND 7 (Not to Scale) 22 DVDD
CREF1 8
21 DB8
CREF2 9
20 DB7
AIN(+) 10
19 DB6
AIN() 11
18 DB5
HBEN 12
17 DB4
DB0 13
16 DB3
DB1 14
15 DB2
AD7854/AD7854L
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Commercial (S Version) . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . +300°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latchup.
Model
ORDERING GUIDE
Temperature
Range1
Linearity
Error
(LSB)
Power
Dissipation
(mW)
Package
Option2
AD7854AQ
AD7854SQ
AD7854AR
AD7854BR
AD7854ARS
AD7854LAQ3
AD7854LAR3
AD7854LARS3
EVAL-AD7854CB4
EVAL-CONTROL BOARD5
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1
1
1
1/2
1
1
1
1
15
15
15
15
15
5.5
5.5
5.5
Q-28
Q-28
R-28
R-28
RS-28
Q-28
R-28
RS-28
NOTES
1Linearity error refers to the integral linearity error.
2Q = Cerdip; R = SOIC; RS = SSOP.
3L signifies the low power version.
4This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for
evaluation/demonstration purposes.
5This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards
ending in the CB designator. For more information on Analog Devices products and evaluation boards visit our
World Wide Web home page at http://www.analog.com.
REV. B
–5–

5 Page





AD7854 arduino
AD7854/AD7854L
CALIBRATION REGISTERS
The AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read
from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are
addressed (See Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should
not attempt to read from and write to the calibration registers at the same time.
CALSLT1
0
0
1
1
CALSLT0
0
1
0
1
Table IV. Calibration Register Addressing
Comment
This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.
This combination addresses the Offset Register. One register in total.
This combination addresses the Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
When writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
When reading from the calibration registers a write to the con-
trol register is required to set the CALSLT0 and CALSLT1 bits
and also to set the RDSLT1 and RDSLT0 bits to 10 (this
addresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer points to the gain
calibration register upon reset in all but one case, this case
being where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed, the calibration register pointer
is automatically incremented after each full calibration register
write/read operation. The calibration register address pointer is
incremented after the high byte read or write operation in byte
mode. Therefore when reading from or writing to the calibra-
tion registers, the low byte transfer must be carried out first, i.e.,
HBEN is at logic zero. The order in which the 10 calibration
registers are arranged is shown in Figure 5. Read/Write opera-
tions may be aborted at any time before all the calibration
registers have been accessed, and the next control register write
operation resets the calibration register pointer. The flowchart
in Figure 6 shows the sequence for writing to the calibration
registers. Figure 7 shows the sequence for reading from the cali-
bration registers.
When reading from the calibration registers there are always two
leading zeros for each of the registers.
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
YES
FINISHED
NO
Figure 6. Flowchart for Writing to the Calibration Registers
CAL REGISTER
ADDRESS POINTER
CALIBRATION REGISTERS
GAIN REGISTER
(1)
OFFSET REGISTER
(2)
DAC 1ST MSB REGISTER (3)
DAC 8TH MSB REGISTER (10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.
Figure 5. Calibration Register Arrangement
REV. B
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