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PDF AD7851 Data sheet ( Hoja de datos )
| Número de pieza | AD7851 | |
| Descripción | 14-Bit 333 kSPS Serial A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/؎2 LSB DNL—A Grade
285 kSPS Throughput Rate/؎1 LSB DNL—K Grade
A & K Grades Guaranteed to 125؇C/238 kSPS
Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on
Power-Up
Read/Write Capability of Calibration Data
Low Power: 60 mW typ
Power-Down Mode: 5 W typ Power Consumption
Flexible Serial Interface:
8051/SPI/QSPI/ P Compatible
24-Pin DIP, SOIC and SSOP Packages
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive
14-Bit 333 kSPS
Serial A/D Converter
AD7851
AIN (+)
AIN (–)
REFIN/
REFOUT
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AGND
T/H
4.096 V
REFERENCE
BUF
AD7851
COMP
DVDD
DGND
AMODE
CREF1
CREF2
CAL
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
CLKIN
CONVST
BUSY
SLEEP
SERIAL INTERFACE / CONTROL REGISTER
SM1 SM2 SYNC DIN DOUT SCLK POLARITY
GENERAL DESCRIPTION
The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers-up with a set of
default conditions at which time it can be operated as a read-
only ADC. The ADC contains self-calibration and system-
calibration options to ensure accurate operation over time and
temperature and has a number of power-down options for low
power applications.
The AD7851 is capable of 333 kHz throughput rate. The input
track-and-hold acquires a signal in 0.33 µs and features a
pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to VREF, and
–VREF/2 to +VREF/2 centered about VREF/2). Input signal range
is to VDD and the part is capable of converting full-power signals
to 20 MHz.
CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 µW typ). The part is available in 24-
pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small
outline (SOIC) and 24-lead small shrink outline (SSOP) packages.
PRODUCT HIGHLIGHTS
1. Single 5 V supply.
2. Operates with reference voltages from 4 V to VDD.
3. Analog input ranges from 0 V to VDD.
4. System and self-calibration including power-down mode.
5. Versatile serial I/O port.
*Patent pending.
See Page 35 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
AD7851
1.6mA IOL
TO
OUTPUT
PIN
CL
50pF
200µA
IOH
+2.1V
Figure 1. Load Circuit for Digital Output Timing
Specifications
POLARITY PIN LOGIC HIGH
CONVST (I/P)
BUSY (O/P)
t2
t1
tCONVERT
tCONVERT = 3.25µs MAX, t1 = 100ns MIN,
t5 = 30ns MAX, t7 = 30ns MIN
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
t5
3-STATE
t3
1
t6
DB15
t7
t8
DB15
t9
5
t6
6
t10
DB11
DB11
t11
16
t12
DB0
3-STATE
DB0
Figure 2. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
CONVST (I/P)
t1
BUSY (O/P)
t2
tCONVERT = 3.25µs MAX, t1 = 100ns MIN,
t5 = 30ns MAX, t7 = 30ns MIN
tCONVERT
SYNC (O/P)
SCLK (O/P)
DOUT (O/P)
DIN (I/P)
t4
1
t5
3-STATE
DB15
t7
t8
DB15
t9
5
t6
DB11
6
t10
t11
16
DB0
t12
3-STATE
DB11
DB0
Figure 3. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
REV. A
–5–
5 Page 
AD7851
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
Figure 6. Flowchart for Reading the Status Register
MSB
ZERO
BUSY
ZERO
ZERO
ZERO
ZERO PMGT1 PMGT0
RDSLT1 RDSLT0 2/3 MODE
X
CALMD CALSLT1 CALSLT0 STCAL
LSB
Bit Mnemonic
15 ZERO
14 BUSY
13 ZERO
12 ZERO
11 ZERO
10 ZERO
9 PMGT1
8 PMGT0
7 ONE
6 ONE
5 2/3 MODE
4X
3 CALMD
2 CALSLT1
1 CALSLT0
0 STCAL
Status Register Bit Function Description
Comment
This bit is always 0.
Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration
in progress. When this bit is 0, there is no conversion or calibration in progress.
These four bits are always 0.
Power Management Bits. These bits along with the SLEEP pin will indicate if the part is in a power-down
mode or not. See Table VI in Power-Down Section for description.
Both these bits are always 1 indicating it is the status register that is being read. See Table II.
Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in
Interface Mode 1. This bit is reset to 0 after every read cycle.
Don’t care bit.
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a
system calibration is selected (see Table III).
Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in
progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate
which of the calibration registers are addressed for reading and writing (see section on the Calibration
Registers for more details).
REV. A
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7851.PDF ] | |
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