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PDF AD783 Data sheet ( Hoja de datos )
| Número de pieza | AD783 | |
| Descripción | Complete Very High Speed Sample-and-Hold Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Acquisition Time to 0.01%: 250 ns Typical
Low Power Dissipation: 95 mW
Low Droop Rate: 0.02 V/s
Fully Specified and Tested Hold Mode Distortion
Total Harmonic Distortion: –85 dB
Aperture Jitter: 50 ps Maximum
Internal Hold Capacitor
Self-Correcting Architecture
8-Pin Mini Cerdip and SOIC Packages
Complete Very High Speed
Sample-and-Hold Amplifier
AD783*
FUNCTIONAL BLOCK DIAGRAM
VCC 1
IN 2
COMMON 3
X1
8 OUT
7 S/H
6 NC
NC 4
AD783 5 VEE
NC = NO CONNECT
PRODUCT DESCRIPTION
The AD783 is a high speed, monolithic sample-and-hold
amplifier (SHA). The AD783 offers a typical acquisition time
of 250 ns to 0.01%. The AD783 is specified and tested for hold
mode total harmonic distortion with input frequencies up to
100 kHz. The AD783 is configured as a unity gain amplifier
and uses a patented self-correcting architecture that minimizes
hold mode errors and ensures accuracy over temperature. The
AD783 is self-contained and requires no external components
or adjustments.
The AD783 retains the held value with a droop rate of 0.02 µV/
µs. Excellent linearity and hold mode dc and dynamic perfor-
mance make the AD783 ideal for high speed 12- and 14-bit
analog-to-digital converters.
The AD783 is manufactured on Analog Devices’ ABCMOS
process which merges high performance, low noise bipolar
circuitry with low power CMOS to provide an accurate, high
speed, low power SHA.
The J grade device is specified for operation from 0°C to +70°C
and the A grade from –40°C to +85°C. The J and A grades are
available in 8-pin cerdip and SOIC packages. The military
temperature range version is specified for operation from –55°C
to +125°C and is available in an 8-pin cerdip package. For
details refer to the Analog Devices Military Products Databook or
AD783/883B data sheet.
*Protected by U.S. Patent Number 4,962,325.
PRODUCT HIGHLIGHTS
1. Fast acquisition time (250 ns), low aperture jitter (20 ps) and
fully specified hold mode distortion make the AD783 an
ideal SHA for sampling systems.
2. Low droop (0.02 µV/µs) and internally compensated hold
mode error result in superior system accuracy.
3. Low power (95 mW typical), complete functionality and
small size make the AD783 an ideal choice for a variety of
high performance applications.
4. The AD783 requires no external components or adjustments.
5. The AD783 is an excellent choice as a front-end SHA for
high speed analog-to-digital converters such as the AD671,
AD7586, AD674B, AD774B, AD7572 and AD7672.
6. Fully specified and tested hold mode distortion guarantees
the performance of the SHA in sampled data systems.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD783
DEFINITIONS OF SPECIFICATIONS
Acquisition Time—The length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Small Signal Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Full Power Bandwidth—The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 5 V p-p sine wave.
Effective Aperture Delay—The difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. This effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Aperture Jitter—The variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Hold Settling Time—The time required for the output to
settle to within a specified level of accuracy of its final held value
after the hold command has been given.
Droop Rate—The drift in output voltage while in the hold
mode.
Feedthrough—The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset—The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
Sample Mode Offset—The difference between the input and
output signals when the SHA is in the sample mode.
Nonlinearity—The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –2.5 V and +2.5 V.
Gain Error—Deviation from a gain of +1 on the transfer
function of input vs. held output.
Power Supply Rejection Ratio—A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Sampled DC Uncertainty—The internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Mode Noise—The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise—The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Output Drive Current—The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Total Harmonic Distortion (THD)—THD is the ratio of the
rms sum of the first six harmonic components to the rms value
of the measured input signal and is expressed in decibels.
Intermodulation Distortion (IMD)—With inputs consisting
of sine waves at two frequencies, fa and fb, any device with
nonlinearities will create distortion products, of order (m+n), at
sum and difference frequency of mfa± nfb, where m, n = 0, 1, 2,
3. . . . Intermodulation terms are those for which m or n is not
equal to zero. For example, the second order terms are (fa+fb)
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),
(fa+2fb) and (fa–2fb). The IMD products are expressed as the
decibel ratio of the rms sum of the measured input signals to the
rms sum of the distortion terms. The two signals are of equal
amplitude, and peak value of their sums is –0.5 dB from full
scale. The IMD products are normalized to a 0 dB input signal.
FUNCTIONAL DESCRIPTION
The AD783 is a complete, high speed sample-and-hold
amplifier that provides high speed sampling to 12-bit accuracy
in 250 ns.
The AD783 is completely self-contained, including an on-chip
hold capacitor, and requires no external components or adjust-
ments to perform the sampling function. Both input and output
are treated as a single-ended signal, referred to common.
The AD783 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. Below is a block diagram of the
AD783.
VCC 1
8 OUT
IN 2
COMMON 3
X1
7 S/H
6 NC
NC 4
AD783 5 VEE
NC = NO CONNECT
Functional Block Diagram
REV. A
–5–
5 Page | ||
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| PDF Descargar | [ Datasheet AD783.PDF ] | |
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