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PDF AD7801 Data sheet ( Hoja de datos )
| Número de pieza | AD7801 | |
| Descripción | +2.7 V to +5.5 V/ Parallel Input/ Voltage Output 8-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Single 8-Bit DAC
20-Pin SOIC/TSSOP Package
+2.7 V to +5.5 V Operation
Internal and External Reference Capability
DAC Power-Down Function
Parallel Interface
On-Chip Output Buffer Rail-to-Rail Operation
Low Power Operation 1.75 mA max @ 3.3 V
Power-Down to 1 A max @ 25؇C
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
+2.7 V to +5.5 V, Parallel Input,
Voltage Output 8-Bit DAC
AD7801
FUNCTIONAL BLOCK DIAGRAM
D7
D0
INPUT
REGISTER
DAC
REGISTER
I DAC
I/V
VOUT
POWER-ON
WR CONTROL
MUX
RESET
CS LOGIC
AD7801
÷2
AGND
PD CLR LDAC
REFIN VDD
DGND
GENERAL DESCRIPTION
The AD7801 is a single, 8-bit, voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision output
buffer allows the DAC output to swing rail to rail. The AD7801
has a parallel microprocessor and DSP compatible interface with
high speed registers and double buffered interface logic. Data is
loaded to the input register on the rising edge of CS or WR.
Reference selection for the AD7801 can be either an internal
reference derived from the VDD or an external reference applied
at the REFIN pin. The output of the DAC can be cleared by
using the asynchronous CLR input.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consump-
tion is less than 5 mW at 3.3 V, reducing to less than 3 µW in
power-down mode.
The AD7801 is available in a 20-lead SOIC and a 20-lead
TSSOP package.
PRODUCT HIGHLIGHTS
1. Low Power, Single Supply operation. This part operates
from a single +2.7 V to +5.5 V supply and consumes typically
5 mW at 3 V, making it ideal for battery powered applications.
2. The on-chip output buffer amplifier allows the output of the
DAC to swing rail to rail with a settling time of typically 1.2 µs.
3. Internal or external reference capability.
4. High speed parallel interface.
5. Power-down capability. When powered down the DAC
consumes less than 1 µA at 25°C.
6. Packaged in 20-lead SOIC and TSSOP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
1 page  
800
720 VDD = 5V AND 3V
INTERNAL REFERENCE
640 TA = +25 C
DAC LOADED WITH 00HEX
560
480
400
320
240
160
80
0
0 24 6
SINK CURRENT – mA
8
Figure 2. Output Sink Current Capa-
bility with VDD = 3 V and VDD = 5 V
0.5
0.45
0.4
VDD = 5V
TA = +25 C
0.35
0.3 INL ERROR
0.25
0.2
0.15
DNL ERROR
0.1
0.05
0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE – Volts
Figure 5. Relative Accuracy vs.
External Reference
10
5
0
–5
–10
–15
–20
–25
–30
VDD = 5V
EXTERNAL SINEWAVE REFERENCE
–35
DAC REGISTER LOADED WITH FFHEX
TA = +25°C
–40
1
10 100 1k 10k
FREQUENCY – Hz
Figure 8. Large Scale Signal
Frequency Response
Typical Performance Characteristics–AD7801
5
4.92
4.84
4.76
4.68
4.6
4.52
4.44
4.36
4.28
VDD = 5V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHEX
TA = +25°C
4.2
0
2 46
SOURCE CURRENT – mA
8
3.5
3.25
3.0
2.75
2.5
2.25
2.0
1.75
1.5
1.25
VDD = 3V
INTERNAL REFERENCE
DAC REGISTER LOADED
WITH FFHex
TA = +25°C
1.0
0
1 2 34 5 6
SOURCE CURRENT – mA
7
8
Figure 3. Output Source Current
Capability with VDD = 5 V
4.0
INTERNAL REFERENCE
3.5
LOGIC INPUTS = VDD OR GND
DAC ACTIVE
3.0
2.5
2.0 VDD = 5.5V
1.5
1.0 VDD = 3.3V
0.5
0
–50 –25 0
25 50 75 100 125
TEMPERATURE – C
Figure 4. Output Source Current
Capability with VDD = 3 V
4.0
DAC ACTIVE
INTERNAL REFERENCE
TA = +25°C
3.0 LOGIC INPUTS = VIH OR VIL
2.0
LOGIC INPUTS = VDD OR GND
1.0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD – Volts
Figure 6. Typical Supply Current
vs. Temperature
Figure 7. Typical Supply Current
vs. Supply Voltage
WR
1←
T
2←
VOUT
VOUT
←
VDD = 3V
INTERNAL VOLTAGE
REFERENCE
FULL SCALE CODE
3←
CHANGE 00H-FFH
TA = +25°C
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200 ns/Div
Figure 9. Full-Scale Settling Time
PD
2←
VOUT
1←
AD7801 POWER-UP TIME
VDD = 5V
INTERNAL REFERENCE
DAC IN POWER-DOWN INITIALLY
CH1 = 2V/div, CH2 = 5V/Div,
TIME BASE = 2 µs/Div
Figure 10. Exiting Power-Down (Full
Power-Down)
REV. 0
–5–
5 Page 
AD7801
In the circuit shown the LDAC is hardwired low thus the DAC
output is updated on the rising edge of WR. Some applications
may require synchronous updating of the DAC in the AD7801.
In this case the LDAC signal can be driven from an external
timer or can be controlled by the microprocessor. One option
for synchronous updating is to decode the LDAC from the ad-
dress bus so a write operation at this address will synchronously
update the DAC output. A simple OR gate with one input
driven from the decoded address and the second input from the
WR signal will implement this function.
AD7801–8051/8088 Interface
Figure 31 shows a serial interface between the AD7801 and the
8051/8088 processors.
A15
ADDRESS BUS
A8
PSEN OR DEN
WR
8051/8088*
ALE
EN ADDR
DECODE
OCTAL
LATCH
AD7801*
CS
WR
LDAC
DB7
DB0
AD7
AD0
DATA BUS
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
Figure 31. AD7801–8051/8088 Interface
APPLICATIONS
Bipolar Operation Using the AD7801
The AD7801 has been designed for unipolar operation but
bipolar operation is possible using the circuit in Figure 32. The
circuit shown is configured for an output voltage range of –5 V
to +5 V. Rail-to-rail operation at the amplifier output is achievable
by using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
( )VO
=
R2
1+
R4
R3
/
R1+ R2
×
2V REF
256
D
−V
REF
R4
R3
Where D is the decimal equivalent of the code loaded to the
DAC and VREF is the reference voltage input.
With VREF = 2.5 V, R1 = R3 = 10 kΩ and R2 = R4 = 20 kΩ and
VDD = 5 V.
VO
=
10D
256
–5
VDD = 3V TO 5V
0.1F 10F
R3
10kΩ
VIN
EXT REF VOUT
GND
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 3V
VDD AGND DGND
REF IN
0.1F
VOUT
AD7801
CLR
PD
D7-D0 CS WR LDAC
VDD
R1
10kΩ
R2
20kΩ
DATA CONTROL
BUS INPUTS
R4
20kΩ
+5V
AD820/
OP295
±5V
–5V
Figure 32. Bipolar Operation Using the AD7801
Decoding Multiple AD7801s in a System
The CS pin on the AD7801 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same input data, but only the CS to one of
the DACs will be active at any one time allowing access to one
channel in the system. The 74HC139 is used as a two-to-four
line decoder to address any of the DACs in the system. To
prevent timing errors from occurring, the Enable input on the
74HC139 should be brought to its inactive state while the
Coded Address inputs are changing state. Figure 33 shows a
diagram of a typical setup for decoding multiple AD7801
devices in a system. The built-in power-on reset circuit on the
AD7801 ensures that the outputs of all DACs in the system
power up with zero volts on their outputs.
DATA BUS
WR
VDD
ENABLE
CODED
ADDRESS
1G
VCC
1Y0
1A 1Y1
1B
1Y2
74HC139
1Y3
DGND
AD7801
CS
WR
D0
D7 LDAC
VOUT
AD7801
CS
WR
D0
D7 LDAC
VOUT
AD7801
CS
WR
D0
D7 LDAC
VOUT
AD7801
CS
WR
D0
D7 LDAC
VOUT
Figure 33. Decoding Multiple AD7801s
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7801.PDF ] | |
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