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PDF AD7777 Data sheet ( Hoja de datos )

Número de pieza AD7777
Descripción LC2MOS/ High Speed 1-/ 4- & 8-Channel 10-Bit ADCs
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
LC2MOS, High Speed
1-, 4- & 8-Channel 10-Bit ADCs
AD7776/AD7777/AD7778*
FEATURES
AD7776: Single Channel
AD7777: 4-Channel
AD7778: 8-Channel
Fast 10-Bit ADC: 2.5 s Worst Case
+5 V Only
Half-Scale Conversion Option
Fast Interface Port
Power-Down Mode
APPLICATIONS
HDD Servos
Instrumentation
GENERAL DESCRIPTION
The AD7776, AD7777 and AD7778 are a family of high speed,
multichannel, 10-bit ADCs primarily intended for use in R/W
head positioning servos found in high density hard disk drives.
They have unique input signal conditioning features that make
them ideal for use in such single supply applications.
By setting a bit in a control register within both the four-channel
version, AD7777, and the eight-channel version, AD7778, the
input channels can either be independently sampled or any two
channels of choice can be simultaneously sampled. For all ver-
sions the specified input signal range is of the form VBIAS ±
VSWING. However, if the RTN pin is biased at, say, 2 V the
analog input signal range becomes 0 V to +2 V for all input
channels. This is covered in more detail under the section
Changing the Analog Input Voltage Range. The voltage VBIAS
is the offset of the ADC’s midpoint code from ground and is
supplied either by an onboard reference available to the user
(REFOUT) or by an external voltage reference applied to
REFIN. The full-scale range (FSR) of the ADC is equal to
2 VSWING where VSWING is nominally equal to REFIN/2. Addi-
tionally, when placed in the half-scale conversion mode, the
value of REFIN is converted. This allows the channel offset(s)
to be measured.
Control register loading and ADC register reading, channel se-
lect and conversion start are under the control of the µP. The
twos complemented coded ADCs are easily interfaced to a stan-
dard 16-bit MPU bus via their 10-bit data port and standard
microprocessor control lines.
The AD7776/AD7777/AD7778 are fabricated in linear compat-
ible CMOS (LC2MOS), an advanced, mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. The AD7776 is available in a 24-pin SOIC package; the
AD7777 is available in both 28-pin DIP and 28-pin SOIC pack-
ages; the AD7778 is available in a 44-pin PQFP package.
*Protected by U.S. Patent No. 4,990,916.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
CLKIN
VCC
AIN1
RTN
MUX
REFIN
CONTROL
REGISTER
10
10-BIT
ADCREG1
T/H ADC
10
DB0–DB9
CREFIN
VBIAS
REFIN
CONTROL LOGIC
VSWING
AGND
REF
AD7776
REFOUT
CS RD WR BUSY/INT
DGND
AGND
CLKIN
VCC
AIN1
AIN2
AIN3
AIN4
MUX T/H
11
CONTROL
REGISTER
10-BIT
ADC
ADCREG2
10
ADCREG1
10
DB0–DB9
CREFIN
VBIAS
REFIN
RTN
REFIN
MUX
2
T/H
2
VSWING
AGND
REF
CONTROL LOGIC
AD7777
REFOUT
DGND AGND
CLKIN
VCC
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
MUX T/H
11
CONTROL
REGISTER
10-BIT
ADC
ADCREG2
10
ADCREG1
10
DB0–DB9
CREFIN
VBIAS
REFIN
RTN
REFIN
MUX
2
T/H
2
VSWING
AGND
REF
CONTROL LOGIC
AD7778
REFOUT
CS RD WR BUSY/INT DGND AGND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997

1 page




AD7777 pdf
AD7776/AD7777/AD7778
PIN FUNCTION DESCRIPTION
Mnemonic Description
VCC
AGND
DGND
DB0–DB9
BUSY/INT
CS
WR
RD
AIN1–8
REFIN
REFOUT
CREFIN
RTN
+5 V Power Supply.
Analog Ground.
Digital Ground. Ground reference for digital circuitry.
Input/Output Data Bus. This is a bidirectional data port from which ADC output data may be read and to which
control register data may be written.
Busy/Interrupt Output. Active low logic output indicating A/D converter status. This logic output has two modes
of operation depending on whether location CR9 of the control register has been set low or high:
If CR9 is set low, then the BUSY/INT output will behave as a BUSY signal. The BUSY signal will go low and stay
low for the duration of a single conversion, or if simultaneous sampling has been selected, BUSY will stay low for
the duration of both conversions.
If CR9 is set high, then the BUSY/INT output behaves as an INTERRUPT signal. The INT signal will go low
and remain low after either a single conversion is completed or after a double conversion is completed if simulta-
neous sampling has been selected. With CR9 high, the falling edge of WR or RD resets the INT line high.
Chip Select Input. The device is selected when this input is low.
Write Input (Active Low). It is used in conjunction with CS to write data to the control register. Data is latched to the
registers on the rising edge of WR. Following the rising edge of WR, the analog input is acquired and a conversion is
started.
Read Input (Active Low). It is used in conjunction with CS to enable the data outputs from the ADC registers.
Analog Inputs 1–8. The analog input range is VBIAS ± VSWING where VBIAS and VSWING are defined by the reference
voltage applied to REFIN. Input resistance between any of the analog input pins and AGND is 10 kor greater.
Voltage Reference Input. The AD7776/AD7777/AD7778 are specified over a voltage reference range of 1.9 V to 2.1 V
with a nominal value of 2.0 V. This REFIN voltage provides the VBIAS and VSWING levels for the input channel(s).
VBIAS is equal to REFIN and VSWING is nominally equal to REFIN/2. Input resistance between this REFIN pin and
AGND is 10 kor greater.
Voltage Reference Output. The internal voltage reference, which is nominally 2.0 V and can be used to provide the
bias voltage (VBIAS) for the input channel(s), is provided at this pin.
Reference Decoupling Capacitor. A 10 nF capacitor must be connected from this pin to AGND to ensure correct
operation of the high speed ADC.
Signal Return Path for the input channel(s). Normally RTN is connected to AGND at the package.
CIRCUIT DESCRIPTION
ADC Transfer Function
For all versions, an input signal of the form VBIAS ± VSWING is
expected. This VBIAS signal level operates as a pseudo ground to
which all input signals must be referred. The VBIAS level is de-
termined by the voltage applied to the REFIN pin. This can be
driven by an external voltage source or, alternatively, the on-
board 2 V reference, available at REFOUT, can be used. The
magnitude of the input signal swing is equal to VBIAS/2 (or
REFIN/2) and is set internally. With a REFIN of 2 V, the analog
input signal level varies from 1 V up to 3 V i.e., 2 ± 1 V. Fig-
ure 5 shows the transfer function of the ADC and its relation-
ship to VBIAS and VSWING. The half-scale twos complement code
of the ADC, 000 Hex (00 0000 0000 Binary), occurs at an input
voltage equal to VBIAS. The input full-scale range of the ADC is
equal to 2 VSWING, so that the Plus Full-Scale transition (1FE to
1FF) occurs at a voltage equal to VBIAS + VSWING – 1.5 LSBs
and the minus full-scale code transition (200 to 201) occurs at
a voltage VBIAS – VSWING + 0.5 LSBs.
1FF
1FE
ADC
OUTPUT
CODE
(HEX)
000
202
201
200
VBIAS –VSWING
VBIAS
ANALOG INPUT, VIN
VBIAS +VSWING
Figure 5. ADC Transfer Function
REV. 0
–5–

5 Page





AD7777 arduino
AD7776/AD7777/AD7778
Changing the Analog Input Voltage Range
By biasing the RTN pin above AGND it is possible to change
the analog input voltage range from its VBIAS ± VSWING format to
a more traditional 0 V to VREF range. The new input range can
be described as
VOFFSET to (VOFFSET + REFIN)
where 0 V VOFFSET 1 V. To produce this range the RTN pin
must be biased to (REFIN – 2 VOFFSET). For instance if
RTN is tied to REFOUT then the analog input range becomes
0 V to 2 V. The fixed 2 V analog input voltage span of the ADC
can range from 1 V to 3 V (RTN = 0 V) to 0 V to 2 V (RTN =
2 V), i.e., with proper biasing, an input signal range from 0.3 V
to 2.3 V can be covered. Both the relative accuracy and differen-
tial nonlinearity performance remains essentially unchanged in
this mode while the SNR and THD performance are typically
2 dB to 3 dB worse than standard.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
R-24
24-Lead Wide-Body SOIC
24
0.299 (7.6)
0.291 (7.4)
PIN 1
1
13
0.419 (10.65)
0.394 (10.00)
12
0.012 (0.3)
0.004 (0.1)
0.614 (15.6)
0.598 (15.2)
0.050 (1.27)
BSC
0.019 (0.49)
0.014 (0.35)
0.104 (2.65)
0.093 (2.35)
0.013 (0.32)
0.009 (0.23)
R-28
28-Lead Wide-Body SOIC
0.005 (1.27)
0.015 (0.40)
28
0.299 (7.60)
0.291 (7.39)
PIN 1
1
0.01 (0.254)
0.006 (0.15)
15
0.414 (10.52)
0.398 (10.10)
14
0.708 (18.02)
0.696 (17.67)
0.096 (2.44)
0.089 (2.26)
0.03 (0.76)
0.02 (0.51)
0.050 (1.27)
BSC
0.019 (0.49)
0.014 (0.35)
0.013 (0.32)
0.009 (0.23)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. SOIC LEADS WILL BE EITHER TIN PLATED OF SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
0.042 (1.067)
0.018 (0.457)
REV. 0
–11–

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