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PDF AD7769 Data sheet ( Hoja de datos )
| Número de pieza | AD7769 | |
| Descripción | LC2MOS Analog I/O Port | |
| Fabricantes | Analog Devices | |
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FEATURES
Two-Channel, 8-Bit 2.5 s ADC
Two 8-Bit, 2.5 s DACs with Output Amplifiers
Span and Offset of ADC and DAC
Independently Adjustable
Low Power
APPLICATIONS
Winchester Disk Servo Controllers
Floppy Disk Microstepping
Closed Loop Servo Systems
LC2MOS
Analog I/O Port
AD7769
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7769 is a complete, two-channel, 8-bit, analog I/O port.
It has versatile input and output signal conditioning features
that make it ideal for use in head-positioning servos in Winches-
ter disk systems. It is equally suitable for floppy disk microstep-
ping head positioning, other closed loop digital servo systems
and general purpose 8-bit data acquisition.
The AD7769 contains a high speed successive approximation
ADC, preceded by a two-channel multiplexer and signal condi-
tioning circuits. The input span of the ADC and the offset of
the zero point from ground can be independently set by apply-
ing ground referenced voltages. The AD7769 also contains two
independent, fast settling, 8-bit DACs with output amplifiers.
The output span and offset voltage of the DACs can be set inde-
pendently of those of the ADC. This makes the AD7769 espe-
cially useful in disk drives, where only a positive supply rail is
available and the ranges of the ADC and DACs must be refer-
enced to some positive voltage less than the supply.
The AD7769 is easily interfaced to a standard 8-bit mpu bus via
an 8-bit data port and standard microprocessor control lines.
The AD7769 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
The part is available in a 28-lead plastic DIP and 28-terminal
PLCC package.
PRODUCT HIGHLIGHTS
1. Two-Channel, 8-Bit Analog I/O port on a Single Chip.
The AD7769 contains a two-channel, high speed ADC with
input signal conditioning and two, fast settling 8-bit DACs
with output amplifiers, on a single chip.
2. Independent Control of Span and Offset.
The input voltage span of the ADC and the midpoint of the
transfer function, the output voltage swing of the two DACs
and the half-scale output voltage, can be set independently
by applying ground referenced control voltages.
3. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7769 is specified with ac parameters including signal-
to-noise ratio, distortion and signal bandwidth.
4. Fast Microprocessor Interface.
The AD7769 has bus interface timing compatible with all
modern microprocessors, with bus access and relinquish
times less than 65 ns and a Write pulse width less than 90 ns.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.comFax:
617/326-8703
© Analog Devices, Inc., 1997
1 page  
AD7769
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND or DGND . . . . . . . . . . . . . . . . . –0.3 V, +15 V
VCC to DGND . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V or 7 V
(Whichever is Lower)
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Digital Inputs to DGND
(Pins 12, 13, 15–18) . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Digital Outputs to DGND
(Pins 3–10, 11) . . . . . . . . . . . . . . . . . . . –0.3 V, VCC +0.3 V
Analog Inputs to AGND . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Analog Outputs to AGND . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Power Dissipation (Any Package)
to +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Derates Above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7769 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature
Range
AD7769JN
AD7769JP
AD7769AN
AD7769AP
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
*N = Plastic DIP; P = Plastic Leaded Chip Carrier.
Package
Option*
N-28
P-28A
N-28
P-28A
NOTE
Do not allow VCC to exceed VDD by more than 0.3 V. In cases
where this can happen the diode protection scheme shown
below is recommended.
PIN CONFIGURATIONS
DIP PLCC
REV. A
–5–
5 Page 
This is for an ideal part with no differential or integral linearity
errors. These errors will cause a degradation in SNR. By work-
ing backwards from the above equation, it is possible to get a
measure of ADC performance expressed in effective number of
bits (N). The effective number of bits is plotted versus fre-
quency in Figure 15. The effective number of bits typically falls
between 7.7 and 7.9, corresponding to SNR Figures 48.1 and
49.7 dB.
AD7769
where A is the peak amplitude of the sine wave and p (V) the
probability of occurrence at a voltage V. The histogram plot of
Figure 17 corresponds very well with this shape.
Figure 15. Effective Number of Bits vs. Frequency
Figure 16 shows a spectrum analyzer plot of the output spec-
trum from one of the DACs with an ideal sine wave table loaded
to the data inputs of the DAC. In this case, the SNR is 47 dB.
Figure 16. DAC Output Spectrum
Histogram Plot
When a sine wave of specified frequency is applied to the VINA
or VINB input of the AD7769 and several thousand samples are
taken, it is possible to plot a histogram showing the frequency of
occurrence of each of the 256 ADC codes. If a particular step is
wider than the ideal 1 LSB width, then the code associated with
that step will accumulate more counts than for the code for an
ideal step. Likewise, a step narrower than ideal width will have
fewer counts. Missing codes are easily seen because a missing
code means zero counts for a particular code. The absence of
large spikes in the plot indicates small differential nonlinearity.
Figure 17 shows a histogram plot for the ADC indicating very
small differential nonlinearity and no missing codes for an input
frequency of 204 kHz. For a sine wave input, a perfect ADC
would produce a probability density function described by the
equation:
1
p (V) = π( A2 –V 2)1/2
Figure 17. ADC Histogram Plot
In digital signal processing applications, where the AD7769 is
used to sample ac signals, it is essential that the signal sampling
occurs at exactly equal intervals. This minimizes errors due to
sampling uncertainty or jitter. A precise timer or clock source,
to start the conversion process, is the best method of generating
equidistant sampling intervals.
MICROPROCESSOR/MICROCOMPUTER INTERFACING
The AD7769 is designed for easy interfacing to microprocessors
and microcomputers as a memory mapped peripheral or an I/O
device. In addition, the AD7769 high speed bus timing allows
direct interfacing to many DSP processors such as the
TMS320C10 and ADSP-2101.
AD7769–TMS320C10 Interface
A typical interface to the TMS320C10 is shown in Figure 18.
The AD7769 is mapped at a port address, and the interface is
designed for the maximum TMS320C10 clock frequency of
20 MHz.
Figure 18. AD7769 to TMS320C10 Interface
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7769.PDF ] | |
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