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PDF ADP1073 Data sheet ( Hoja de datos )

Número de pieza ADP1073
Descripción Micropower DC.DC Converter Adjustable and Fixed 3.3 V/ 5 V/ 12 V
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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No Preview Available ! ADP1073 Hoja de datos, Descripción, Manual

a
Micropower DC–DC Converter
Adjustable and Fixed 3.3 V, 5 V, 12 V
ADP1073
FEATURES
Operates at Supply Voltages from 1.0 V to 30 V
Ground Current 100 A
Works in Step-Up or Step-Down Mode
Very Few External Components Required
Low Battery Detector On-Chip
User-Adjustable Current Limit
Internal 1 A Power Switch
Fixed and Adjustable Output Voltage Versions
8-Lead DIP or SO-8 Package
APPLICATIONS
Single-Cell to 5 V Converters
Laptop and Palmtop Computers
Pagers
Cameras
Battery Backup Supplies
Cellular Telephones
Portable Instruments
4 mA–20 mA Loop Powered Instruments
Hand-Held Inventory Computers
GENERAL DESCRIPTION
The ADP1073 is part of a family of step-up/step-down switch-
ing regulators that operates from an input supply voltage of as
little as 1.0 V. This extremely low input voltage allows the
ADP1073 to be used in applications requiring use of a single
cell battery as the primary power source.
The ADP1073 can be configured to operate in either step-up or
step-down mode but for input voltages greater than 3 V, the
ADP1173 is recommended.
An auxiliary gain amplifier can serve as a low battery detector or
linear regulator. Quiescent current on the ADP1073-5 is only
100 µA unloaded, making it ideal for systems where long battery
life is required.
The ADP1073 can deliver 40 mA at 5 V from an input voltage
range as low as 1.25 V, or 10 mA at 5 V from a 1.0 V input.
Current limiting is available by adding an external resistor.
FUNCTIONAL BLOCK DIAGRAMS
SET
VIN
212mV
REFERENCE
A2
GAIN BLOCK/
ERROR AMP
ADP1073
A1 OSCILLATOR
COMPARATOR
DRIVER
GND
FB
AO
ILIM
SW1
SW2
ADP1073
SET
VIN
212mV
REFERENCE
ADP1073-3.3
ADP1073-5
ADP1073-12
A2
GAIN BLOCK/
ERROR AMP
A1 OSCILLATOR
AO
ILIM
SW1
R1
GND
COMPARATOR
DRIVER
R2
904k
ADP1073-3.3: R1 = 62.1k
ADP1073-5: R1 = 40k
ADP1073-12: R1 = 16.3k
SENSE
ADP1073-3.3, 5, 12
SW2
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997

1 page




ADP1073 pdf
2300
2100
1900
VIN = 1.5V
RL = 100k
1700
1500
1300
1100
؊40
0 25 70
TEMPERATURE – ؇C
85
Figure 11. “Gain Block” Gain vs. Temperature
ADP1073
THEORY OF OPERATION
The ADP1073 is a flexible, low power switch mode power
supply (SMPS) controller. The regulated output voltage can be
greater than the input voltage (boost or step-up mode) or less
than the input (buck or step-down mode). This device uses a
gated-oscillator technique to provide very high performance
with low quiescent current.
A functional block diagram of the ADP1073 is shown on the
front page. The internal 212 mV reference is connected to one
input of the comparator, while the other input is externally
connected (via the FB pin) to a feedback network connected to
the regulated output. When the voltage at the FB pin falls below
212 mV, the 19 kHz oscillator turns on. A driver amplifier pro-
vides base drive to the internal power switch and the switching
action raises the output voltage. When the voltage at the FB pin
exceeds 212 mV, the oscillator is shut off. While the oscillator is
off, the ADP1073 quiescent current is only 100 µA. The com-
parator includes a small amount of hysteresis, which ensures
loop stability without requiring external components for fre-
quency compensation.
The maximum current in the internal power switch can be set
by connecting a resistor between VIN and the ILIM pin. When
the maximum current is exceeded, the switch is turned OFF.
The current limit circuitry has a time delay of about 2 µs. If an
external resistor is not used, connect ILIM to VIN. Further infor-
mation on ILIM is included in the Limiting the Switch Current
section of this data sheet.
The ADP1073 internal oscillator provides 38 µs ON and 15 µs
OFF times, which is ideal for applications where the ratio be-
tween VIN and VOUT is roughly a factor of three (such as gener-
ating +5 V from a single 1.5 V cell). Wider range conversions,
as well as step-down converters, can also be accomplished with
a slight loss in the maximum output power that can be obtained.
An uncommitted gain block on the ADP1073 can be connected
as a low-battery detector, linear post-regulator or undervoltage
lockout detector. The inverting input of the gain block is inter-
nally connected to the 212 mV reference. The noninverting
input is available at the SET pin. A resistor divider, connected
between VIN and GND with the junction connected to the SET
pin, causes the AO output to go LOW when the input voltage
goes below the low battery set point. The AO output is an open
collector NPN transistor that can sink 100 µA.
The ADP1073 provides external connections for both the col-
lector and emitter of its internal power switch, which permits
both step-up and step-down modes of operation. For the step-
up mode, the emitter (Pin SW2) is connected to GND and the
collector (Pin SW1) drives the inductor. For step-down mode,
the emitter drives the inductor while the collector is connected
to VIN.
The output voltage of the ADP1073 is set with two external
resistors. Three fixed-voltage models are also available:
ADP1073-3.3 (+3.3 V), ADP1073-5 (+5 V) and ADP1073-12
(+12 V). The fixed-voltage models are identical to the ADP1073,
except that laser-trimmed voltage-setting resistors are included
on the chip. Only three external components are required to
form a +3.3 V, +5 V or +12 V converter. On the fixed-voltage
models of the ADP1073, simply connect the feedback pin (Pin
8) directly to the output voltage.
The ADP1073 oscillator only turns on when the output voltage
is below the programmed voltage. When the output voltage is
above the programmed voltage, the ADP1073 remains in its
quiescent state to conserve power. Output ripple, which is in-
herent in gated oscillator converters, is typically 125 mV for a
5 V output and 300 mV for a 12 V output. This ripple voltage
can be greatly reduced by inserting the gain-block between the
output and the FB pin. Further information and a typical circuit
are shown in the Programming the Gain Block section.
REV. 0
–5–

5 Page





ADP1073 arduino
VIN
ADP1073 Q3
RLIM
(EXTERNAL)
ILIM
R1
80
(INTERNAL)
SW1
OSCILLATOR
DRIVER
Q2
Q1
SW2
Figure 21. Current Limit Operation
Programming the Gain Block
The gain block of the ADP1073 can be used as a low battery
detector, error amplifier or linear post regulator. The gain block
consists of an op amp with PNP inputs and an open-collector
NPN output. The inverting input is internally connected to the
ADP1073’s 212 mV reference, while the noninverting input is
available at the SET pin. The NPN output transistor will sink
about 100 µA.
Figure 22a shows the gain block configured as a low-battery
monitor. Resistors R1 and R2 should be set to high values to
reduce quiescent current, but not so high that bias current in
the SET input causes large errors. A value of 100 kfor R2 is a
good compromise. The value for R1 is then calculated from the
formula:
R1 = V LOBATT 212 mV
212 mV
R2
where VLOBATT is the desired low battery trip point. Since the
gain block output is an open-collector NPN, a pull-up resistor
should be connected to the positive logic power supply.
+5V
VBAT
R1 ADP1073
212mV
SET REF
VIN
AO
100k
TO
PROCESSOR
GND
R2
( )R1 = R2 VLB –1
212mV
VLB = BATTERY TRIP POINT
Figure 22a. Setting the Low Battery Detector Trip Point
ADP1073
+5V
VBAT
R1
R2
33k
ADP1073
212mV
SET REF
GND
VIN
AO
47k
TO
PROCESSOR
R3
1.6M
Figure 22b. Adding Hysteresis to the Low Battery Detector
The circuit of Figure 22a may produce multiple pulses when
approaching the trip point, due to noise coupled into the SET
input. To prevent multiple interrupts to the digital logic, hyster-
esis can be added to the circuit (Figure 22b). Resistor RHYS, with
a value of 1 Mto 10 M, provides the hysteresis. The addi-
tion of RHYS will change the trip point slightly, so the new value
for R1 will be:
R1= V LOBATT – 212 mV

212 mV
R2

VRL L+21R2HmYSV

where VL is the logic power supply voltage, RL is the pull-up
resistor and RHYS creates the hysteresis.
The gain block can also be used as a control element to reduce
output ripple. The ADP3000 is normally recommended for low-
ripple applications, but its minimum input voltage is 2 V. The
gain-block technique using the ADP1073 can be useful for step-
up converters operating down to 1 V.
A step-up converter using this technique is shown in Figure 23.
This configuration uses the gain block to sense the output volt-
age and control the comparator. The result is that the compara-
tor hysteresis is reduced by the open loop gain of the gain block.
Output ripple can be reduced to only a few millivolts with this
technique, versus a typical value of 150 mV for a +5 V converter
using just the comparator. For best results, a large output
capacitor (1000 µF or more) should be specified. This tech-
nique can also be used for step-down or inverting applications,
but the ADP3000 is usually a more appropriate choice. See the
ADP3000 data sheet for further details.
VBAT
R3
680k
L1 D1
ILIM VIN
AO
ADP1073
SW1
SET
FB
GND
SW2
R1
R2
VOUT
C1
( ) ( )VOUT =
R1 +1
R2
212mV
Figure 23. Using the Gain Block to Reduce Output Ripple
REV. 0
–11–

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