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PDF 1775 Data sheet ( Hoja de datos )

Número de pieza 1775
Descripción Universal MacAir/1553 Dumb RTU Hybrid PRELIMINARY DATA SHEET
Fabricantes Aeroflex Circuit Technology 
Logotipo Aeroflex Circuit Technology Logotipo



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No Preview Available ! 1775 Hoja de datos, Descripción, Manual

CT 1775
Universal MacAir/1553 Dumb RTU Hybrid
PRELIMINARY DATA SHEET
www.aeroflex.com/Avionics
FEATURES
CT1775 Replaces DDC BUS-65201
Includes:
- Universal Transceiver
- Encoder/decoder
- Dual Rank I/O Registers
- Fail-safe Timer
- Clock Oscillator
Simple Controls for Single or Dual Redundant Data Bus Configurations
Provides Flags for:
- Own Address (With Parity)
- Mode Code
- Broadcast
- Time Out
- Valid Word
- Sync Type
16 Bit or 8 Bit 3-State
- Parallel I/O and Serial Out
Wraparound Built-In Test
MIL-PRF-38534 Compliant Circuits Available
Packaging – Hermetic Metal
- 68 Pin, 1.85" x 1.6" x .19" Plug-In Type Package
DESCRIPTION
The CT1775 Universal MACAIR/1553 Dumb Remote Terminal Unit (RTU) consists of a transceiver, and encoder/decoder, control
logic, dual rank I/O registers and internal clock oscillator packaged in a 1.6" x 1.9" hermetic hybrid. It provides all the functions
required to interface between a MACAIR (sinusodial) or MIL-STD-1553 (Trapezoidal) serial MUX data bus and a subsystem parallel
3-state data highway. Utilizing several ASIC ICs, the CT1775 provides sufficient handshaking, control and data lines to permit
versatile operation as a remote terminal, a bus controller or a bus monitor, in either single or dual redundant data bus configurations.
As a transmitter, the CT1775 accepts 8 bit or 16 bit parallel date from the subsystem, and outputs serial Manchester II coded
Command, Status or Data words, under subsystem control. As a receiver, it accepts serial MIL-STD-1553 or MACAIR transmissions
and transfers all Command, Status and Data words to the 8 bit or 16 bit data highway, under subsystem control. The CT1775 also
provides flags to the subsystem when Broadcast, Mode Code, and Own Address (with parity) commands are decoded.
The CT1775 contains a terminal fail-safe timeout circuit which flags message lengths exceeding 768µs, and terminates serial data
transmission. Wraparound selftest is initiated by a control line which causes the encoder serial output to be connected to the decoder
input. The CT1775 provides a serial output of decoded words, thus allowing Command Word look ahead, for the fastest terminal
response.
SCDCT1775 Rev B

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1775 pdf
OUTPUT FLAGS
The CT1775 provides numerous output flags to offer the
greatest user flexibility. VALID WORD indicates receipt of a
word with valid sync, Manchester coding and parity. RT
ENABLE indicates a valid word and correct address. VAL
CMD WD indicates a valid word and a Command Sync.
BROADCAST indicates a valid command word and an address
of 11111. The BROADCAST flag may be inhibited by using
the BDCST INHIBIT line. MODE CODE indicates a valid
command word and a subaddress of 11111 or 00000.
INITIALIZATION
To ensure error-free operation, it is desirable to reset the
CT1775 to its initialized state upon power turn-on. The MRST
(master reset) signal is provided for this purpose. Both the
flecoder and encoder, as well as all flags, are reset by a LOW
on MRST. This function interrupts and overrides all other
control signals. The MRST function can also be sued during
fault recovery routines.
TRANSCEIVER OPERATION
The CT1775 contains a transceiver similar to Aeroflex model
CT3232. When connected to a serial MUX data bus via
transformer and isolation resistors, as shown in Figure 6, the
CT1775 transceiver will fully comply with MIL-STD-1553.
The correct Technitrol part numbers for transformers used in
direct-coupled and transformercoupled operation are shown in
Figure 6.
Transceiver TX INHIBIT and RX STROBE signals are
provided to afford flexible operation. These signals may be
used to disable the transmitter and receiver, respectively.
ENCODER OPERATION
Figure 2 illustrates the transmit mode timing. Encoder detail
timing is shown in Figure 4. The transmit cycle is initiated by a
LOW on ENC ENABLE. The first HIGH to LOW (falling
edge) transition of ESC OUT, when ENC ENABLE is LOW,
starts the cycle which lasts for 20 clock periods of the 1 MHz
ESC OUT. The next LOW to HIGH transition of ESC OUT
strobes the SYNC SELECT line. A HIGH on SYNC SELECT
produces a data sync and a LOW produces a command/status
sync.
A LOW to HIGH transition of SEND DATA occurs at the
fourth falling edge of ESC OUT. This indicates the completion
of the sync interval and the start of the serial data interval.
Parallel data must be stable at the second rank transmit register
prior to the rising edge of SEND DATA, which occurs 3
microseconds (minimum) after the HIGH to LOW transition of
ENC ENABLE. LATCH DATA is used to transfer parallel data
to the first rank transmit register. LATCH DATA must be
brought LOW and DATA SELECT brought HIGH prior to the
rising edge of SEND DATA. If SEND DATA is connected
directly to LOAD DATA, it will lock out the second rank
transmit register and serial data shifting into the encoder will
proceed properly.
For multiple word transmissions, the next word may be
transferred to the transmit register any time after SEND DATA
goes HIGH, but no later than the next LOW to HIGH transition
of SEND DATA. SEND DATA remains HIGH for 16 periods
of ESC OUT, during which time the data word is serially
shifted to the Manchester encoder. The encoder adds the parity
bit during the next ESC OUT period after SEND DATA goes
LOW. To terminate transmission after any word, ENC
ENABLE must go to HIGH no later than the first rising edge of
ESC OUT after SEND DATA goes LOW.
The entire transmit cycle may be interrupted and initialized by
applying a 1 microsecond (minimum) negative pulse to MRST.
It is possible to input data to the encoder in serial form by
forcing both transmit registers to be transparent. With LATCH
DATA 1 held HIGH and LOAD DATA 1 held LOW, serial data
input on D15 will be applied directly to the encoder serial
input. ESC OUT must be used to shift in the serial data, MSB
first, starting at the LOW to HIGH transition of SEND DATA.
DECODER OPERATION
Figure 3 illustrates the receive mode timing. Decoder detail
timing is shown in Figure 5. A receive cycle, which lasts for 20
clock periods of the 1 MHz DSC OUT, is initiated when the
decoder recognizes a valid sync and two valid Manchester data
bits. TAKE DATA goes LOW at the first HIGH to LOW
(falling edge) transition of DSC OUT, following the second
valid dat bit. COMM/DATA SYNC is updated at the next
rising edge of DSC OUT after TAKE DATA goes LOW.
COM/DATA SYNC remains in its new state until the next valid
word or until DEC RST or MRST goes LOW.
TAKE DATA remains LOW for 16 periods of DSC OUT,
during which time the 16 serial data bits are shifted into the
first rank receive register. The serial data is simultaneously
available at SERIAL DATA OUT as it is being shifted. At the
completion of decoded data shifting, TAKE DATA goes HIGH,
which transfers the data to the second rank receive register.
This data may be enabled onto the parallel data highway by
LOW on DATA SELECT at any time until the next rising edge
of TAKE DATA.
At the first rising edge of DSC OUT after TAKE DATA goes
HIGH, VALID WORD is updated. It will go LOW if the
decoded word was valid. VALID WORD will go HIGH at the
start of the next receive cycle, or after 20 microseconds if no
additional words ar received. All output flags are enabled by
VALID WORD, and therefore they are valid only as long as
VALID WORD is LOW.
SCDCT1775 Rev B
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1775 arduino
PIN
#
NAME
39 D13
40 D11
41 D9
42 D7
43 D5
44 D3
45 D1
46 LOAD DATA 2
47 +5V
48 +12V
49 RX DATA IN
50 RX STROBE
51 TX DATA OUT
52 CASE
53 DATA SELECT 2
54 DATA SELECT 1
55 ENA PAR CHECK
56 D14
57 D12
58 D10
59 D8
60 D6
61 D4
62 D2
63 D0
64 LOAD DATA 1
65 GND
PIN FUNCTION AND LOADING TABLE (con’t)
IIH IIL IOH IOL
(µA) (mA) (mA) (mA)
DESCRIPTION
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.4
LOW on this input causes the data of the D0 through D7
outputs of the first rank transmit register to be loaded into
the second rank transmit register. A HIGH locks out the
second rank register inputs.
+5V power supply input.
+12Vpower supply input.
Inverted receiver input.
40 -1.6
A LOW on this input disables the receiver output.
Transmitter output.
Case connection.
20 -0.4
A LOW on this input causes the output of the second rank
receiver register to appear on D0 through D7 of the parallel
tri-state I/O.
20 -0.4
A LOW on this input causes the output of the second rank
receiver register to appear on D8 through D15 of the
parallel tri-state I/O.
20 -0.4
A LOW on this input enables the function of ODD
PARITY.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 Part of 16 bit parallel tri-state I/O.
20 -0.2 -12 12 LSB of 16 bit parallel tri-state I/O.
20 -0.4
A LOW on this input causes the data of the D8 through
D15 outputs of the first rank transmit register to be loaded
into the second rank transmit register. A HIGH locks out
the second rank register inputs.
Power supply and logic retum
SCDCT1775 Rev B
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