PDF ADV7129 Data sheet ( Hoja de datos )

Número de pieza	ADV7129
Descripción	192-Bit/ 360 MHz True-Color Video DAC with Onboard PLL
Fabricantes	Analog Devices
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No Preview Available ! a 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL ADV7129 FEATURES 192-Bit Pixel Port Allows 2048 ؋ 2048 ؋ 24 Screen Resolution 360 MHz, 24-Bit True-Color Operation Triple 8-Bit D/A Converters 8:1 Multiplexing Onboard PLL RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs Internal Voltage Reference Standard 8-Bit MPU I/O Interface DAC-DAC Matching: Typ 2%, Adjustable to 0.02% +5 V CMOS Monolithic Construction 304-Pin PQFP Package APPLICATIONS Ultrahigh Resolution Color Graphics Image Processing Drives 24-Bit Color 2K ؋ 2K Monitors GENERAL DESCRIPTION The ADV7129 is a complete analog output, video DAC on a single CMOS (ADV®) monolithic chip. The part is specifically designed for use in the highest resolution graphics and imaging systems. The ultimate level of integration, comprised of 360 MHz triple 8-bit DACs, a programmable pixel port, an internal voltage refer- ence and an onboard PLL, makes the ADV7129 the only choice for the very highest level of performance and functionality. The device consists of three high speed, 8-bit, video D/A con- verters (RGB). An onboard phase locked loop clock generator is provided to provide high speed operation without requiring high speed external crystal or clock circuitry. The part is fully controlled through the MPU port by the on- board command registers. This MPU port may be updated at any time without causing sparkle effects on the screen. ADV is a registered trademark of Analog Devices, Inc. (continued on page 10) VSYNC HSYNC CSYNC BLANK ODD/EVEN A B PIXEL DATA (RED, GREEN, BLUE) C D E F G H LOADIN LPF FUNCTIONAL BLOCK DIAGRAM VAA BLANK AND SYNC LOGIC 24 8 24 24 MUX 24 8:1 8 24 8 24 24 24 ADV7129 RED DAC GREEN DAC BLUE DAC PLL CLOCK CONTROL INT PIXEL CLOCK CONTROL REGISTERS MPU PORT 8 LOADOUT CE R/W C0 C1 D7–D0 VOLTAGE REFERENCE GND SENSE/SYNCOUT IOR IOR IOG IOG IOB IOB VREF RRSET RGSET RBSET RCOMP GCOMP BCOMP ADV is a registered trademark of Analog Devices, Inc.. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 1 page ADV7129 ABSOLUTE MAXIMUM RATINGS1 VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +260°C Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . +220°C Analog Outputs to GND2 . . . . . . . . . . . GND – 0.5 V to VAA Current on Any DAC Output . . . . . . . . . . . . . . . . . . . . 60 mA NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. ORDERING GUIDE* Model Temperature Range Package Option ADV7129KS 0°C to +70°C S-304 *Due to the specialized nature and application of this part, it is not automati- cally available to order. Please contact your local sales office for details. 304-LEAD PQFP PIN CONFIGURATION 228 229 ROW C 153 152 ROW D ADV7129 PQFP TOP VIEW (Not to Scale) ROW B 304 1 PIN NO. 1 IDENTIFIER ROW A 77 76 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7129 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– 5 Page ADV7129 REGISTER PROGRAMMING The following section describes each register, including Address Register and each of the Control Registers in terms of its configuration. Address Register (A10–A0) As illustrated previously, the C1–C0 inputs, in conjunction with the Address Register specify which control register, or palette RAM location is accessed by the MPU port. The Address Reg- ister is 16 bits wide and can be read from as well as written to. CONTROL REGISTERS A large bank of registers can be accessed using the Address reg- ister and C1–C0. Access is made first by writing the Address Register with the appropriate address to point to the particular Control Register, and then performing an MPU access to the Control Register. ADDRESS REGISTER (A10–A0) C1 C0 R/W 00 0 01 0 10 0 00 1 01 1 10 1 11 X WRITE TO ADDRESS REGISTER (LOWER BYTE) WRITE TO ADDRESS REGISTER (UPPER BYTE) WRITE TO REGISTERS READ FROM ADDRESS REGISTER (LOWER BYTE) READ FROM ADDRESS REGISTER (UPPER BYTE) READ FROM REGISTERS RESERVED (A10–A0) 4FF–412 411 410 40F 40E 40D 40C 40B 40A 409 408 407 406 405 004 403 402 401 400 000–3FF REGISTER ACCESS RESERVED COMMAND REGISTER 2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BLUE DAC GAIN ERROR REGISTER GREEN DAC GAIN ERROR REGISTER RED DAC GAIN ERROR REGISTER RESERVED RESERVED RESERVED RESERVED COMMAND REGISTER 1 RESERVED COMMAND REGISTER 1 (CR1) (Address Register (A10–A0) = 400H) This register contains a number of control bits as shown in the diagram. CR1 is an 8-bit wide register. Figure 7 shows the various operations under the control of CR1. This register can be read from as well as written to. Bit CR16 is reserved and should be set to logic “1.” COMMAND REGISTER 1-BIT DESCRIPTION BLANK Control on Inverted Outputs (CR10): This bit specifies whether the video BLANK is to be decoded onto the inverted analog outputs or ignored. SYNC Control on Inverted Outputs (CR11) This bit specifies whether the video SYNC is to be decoded onto the inverted analog outputs or ignored. SYNC Recognition on Blue (CR12) This bit specifies whether the video SYNC input is to be de- coded onto the IOB analog output or ignored. SYNC Recognition on Green (CR13) This bit specifies whether the video SYNC input is to be de- coded onto the IOG analog output or ignored. SYNC Recognition on Red (CR14) This bit specifies whether the video SYNC input is to be de- coded onto the IOR analog output or ignored. Pedestal Enable Control (CR15) This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes- tal is to be generated on the video outputs. Display Mode Control (CR17) This bit controls whether the display is interlaced or noninterlaced. Figure 6. Control Registers CR17 CR16 CR15 CR14 CR13 CR12 CR11 CR10 INTERLACE ENABLE CR17 0 DISABLE 1 ENABLE PEDESTAL ENABLE CONTROL CR15 0 1 0 IRE 7.5 IRE CR16 = 0 (RESERVED) ZERO MUST BE WRITTEN TO THIS BIT SYNC RECOGNITION CONTROL (IOB) PEDESTAL CONTROL (IOR, IOG, IOB) CR12 0 1 IGNORE DECODE SYNC RECOGNITION CONTROL (IOG) CR10 0 1 DISABLE BLANK ON INVERTED OUTPUTS DECODE BLANK ON INVERTED OUTPUTS CR13 0 1 IGNORE DECODE SYNC CONTROL (IOR, IOG, IOB) CR11 SYNC RECOGNITION CONTROL (IOR) CR14 0 IGNORE 1 DECODE 0 DISABLE SYNC ON INVERTED OUTPUTS 1 DECODE SYNC ON INVERTED OUTPUTS Figure 7. Command Register 1 REV. 0 –11– 11 Page

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