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PDF ADV611 Data sheet ( Hoja de datos )

Número de pieza ADV611
Descripción Closed Circuit TV Digital Video Codec
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
Closed Circuit TV Digital
Video Codec
ADV611/ADV612
FEATURES
Programmable “Quality Box”
Industrial Temperature Range (ADV612)
Hardware Frame Rate Reduction
100% Bitstream Compatible with the ADV601 and
ADV601LC
Precise Compressed Bit Rate Control
Field Independent Compression
8-Bit Video Interface Supports CCIR-656 and Multi-
plexed Philips Formats
General Purpose 16- or 32-Bit Host Interface with
512 Deep 32-Bit FIFO
PERFORMANCE
Real-Time Compression or Decompression of CCIR-601
to Video:
720 ؋ 288 @ 50 Fields/Sec — PAL
720 ؋ 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less to 7500:1
Visually Loss-Less Compression At 4:1 on Natural
Images (Typical)
APPLICATIONS
CCTV Cameras and Systems
Time-Lapse Video Tape Recorders
Time-Lapse Video Disk Recorders
Wireless CCTV Cameras
Fiber CCTV Systems
GENERAL DESCRIPTION
The ADV611/ADV612 are low cost, single chip, dedicated func-
tion, all-digital-CMOS-VLSI devices capable of supporting
visually loss-less to 7500:1 real-time compression and decom-
pression of CCIR-601 digital video at very high image quality
levels. The chips integrate glueless video and host interfaces
with on-chip SRAM to permit low part count, system level
implementations suitable for a broad range of applications.
The ADV611/ADV612 are 100% bitstream compatible with
the ADV601. The ADV611/ADV612 comes in a 120-lead
LQFP package.
The ADV611/ADV612 are video encoders/decoders optimized
for closed circuit TV (CCTV) applications. With the ADV611/
ADV612, you can define a portion of each video field to be at a
higher quality level relative to the rest of the field. This “quality
box” feature significantly increases compression of less impor-
tant background details, while retaining the image’s overall
context. Additionally, the unique subband coding architecture
of the ADV611/ADV612 offer many application-specific
advantages. A review of the General Theory of Operation and
Applying the ADV611/ADV612 sections will help you get the
most use out of the ADV611/ADV612 in any given application.
The ADV611/ADV612 accept component digital video through
the Video Interface and outputs a compressed bitstream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV611/ADV612 accept compressed bitstream through the Host
Interface and outputs component digital video through the Video
Interface. The host accesses all of the ADV611/ADV612’s control
and status registers using the Host Interface. Figure 2 summarizes
the basic function of the part.
(continued on page 2)
ANALOG
VIDEO
SIGNAL
OR
IMAGE
SENSOR
SIGNAL
ADV7185
DECODER
DIGITIZER
ADV611/
ADV612
ADSP-21xx
SERIAL
OR PARALLEL
BITSTREAM FOR
TRANSMISSION
OR STORAGE
QUALITY BOX CONTROLS
FROM REMOTE SITE
Figure 1. Typical Application
8
COMPONENT
VIDEO I/O
FUNCTIONAL BLOCK DIAGRAM
ADV611/
ADV612
LOCATION, SIZE AND CONTRAST CONTROL
ON-CHIP
TRANSFORM
BUFFER
SUBBAND STATISTICS
DIGITAL
VIDEO
I/O PORT
QUALITY
BOX
CONTROL
WAVELET
FILTERS,
DECIMATOR &
INTERPOLATOR
QUANTIZER
& ENTROPY
CODING
HOST
I/O PORT
& FIFO
DRAM
MANAGER
BIN WIDTH CONTROL
16/32
HOST
256K ؋ 16-BIT DRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

1 page




ADV611 pdf
ADV611/ADV612
ENCODE
PATH
DECODE
PATH
WAVELET
KERNEL
FILTER BANK
ADAPTIVE
QUANTIZER
RUN LENGTH
CODER &
HUFFMAN
CODER
COMPRESSED
DATA
Figure 4. Encode and Decode Paths
References
For more information on the terms, techniques and underlying
principles referred to in this data sheet, you may find the follow-
ing reference texts useful. A reference text for general digital
video principles is:
Jack, K., Video Demystified: A Handbook for the Digital Engineer
(High Text Publications, 1993) ISBN 1-878707-09-4
Three reference texts for wavelet transform background infor-
mation are:
Vetterli, M., Kovacevic, J., Wavelets And Subband Coding
(Prentice Hall, 1995) ISBN 0-13-097080-8
Benedetto, J., Frazier, M., Wavelets: Mathematics And Applica-
tions (CRC Press, 1994) ISBN 0-8493-8271-8
Grossman, A., Morlet, J., Decomposition of Hardy Functions into
Square Integrable Wavelets of Constant Shape, Siam. J. Math.
Anal., Vol. 15, No. 4, pp 723-736, 1984
THE WAVELET KERNEL
This block contains a set of filters and decimators that work on
the image in both horizontal and vertical directions. Figure 8
illustrates the filter tree structure. The filters apply carefully
chosen wavelet basis functions that better correlate to the broad-
band nature of images than the sinusoidal waves used in Dis-
crete Cosine Transform (DCT) compression schemes (JPEG,
MPEG, and H261).
An advantage of wavelet-based compression is that the entire
image can be filtered without being broken into sub-blocks as
required in DCT compression schemes. This full image filtering
eliminates the block artifacts seen in DCT compression and
offers more graceful image degradation at high compression
ratios. The availability of full image subband data also makes
image processing, scaling, and a number of other system fea-
tures possible with little or no computational overhead.
The resultant filtered image is made up of components of the
original image as is shown in Figure 5 (a modified Mallat Tree).
Note that Figure 5 shows how a component of video would be
filtered, but in multiple component video, luminance and color
components are filtered separately. In Figure 6 and Figure 7 an
actual image and the Mallat Tree (luminance only) equivalent is
shown. It is important to note that while the image has been
filtered or transformed into the frequency domain, no compres-
sion has occurred. With the image in its filtered state, it is now
ready for processing in the second block, the quantizer.
Understanding the structure and function of the wavelet filters
and resultant product is the key to obtaining the highest perfor-
mance from the ADV611/ADV612. Consider the following
points:
The data in all blocks (except N) for all components are high
pass filtered. Therefore, the mean pixel value in those blocks
is typically zero and a histogram of the pixel values in these
blocks will contain a single “hump” (Laplacian distribution).
The data in most blocks is more likely to contain zeros or
strings of zeros than unfiltered image data.
The human visual system is less sensitive to higher frequency
blocks than low ones.
Attenuation of the selected blocks in luminance or color com-
ponents results in control over sharpness, brightness, contrast
and saturation.
High quality filtered/decimated images can be extracted/created
without computational overhead.
Through leverage of these key points, the ADV611/ADV612
not only compresses video, but offers a host of application
features. Please see the Applying the ADV611/ADV612 section
for details on getting the most out of the ADV611/ADV612’s
subband coding architecture in different applications.
NL
MK
J
I
H
G
F
E
C
A
DB
BLOCK A IS HIGH PASS IN X AND DECIMATED BY TWO.
BLOCK B IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK C IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK D IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK E IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK F IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 32.
BLOCK G IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK I IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 128.
BLOCK J IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK K IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK L IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
BLOCK M IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK N IS LOW PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
Figure 5. Modified Mallat Diagram (Block Letters Correspond to Those in Filter Tree)
REV. 0
–5–

5 Page





ADV611 arduino
ADV611/ADV612
ADV611/ADV612 REGISTER DESCRIPTIONS
Indirect Address Register
Direct (Write) Register Byte Offset 0x00.
This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All
indirect write registers are 16 bits wide. The address in this register is auto-incremented on each subsequent access of the indirect
data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width controls.
[15:0] Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through
the indirect data register (undefined at reset).
[31:16] Reserved (undefined read/write zero)
Indirect Register Data
Direct (Read/Write) Register Byte Offset 0x04
This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register.
[15:0] Indirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset.
[31:16] Reserved (undefined read/write zero)
Compressed Data Register
Direct (Read/Write) Register Byte Offset 0x08
This register holds a 32-bit sequence from the compressed video bitstream. This register is buffered by a 512 position, 32-bit FIFO.
For Word (16-bit) accesses, access Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3) for correct auto-increment. For a
description of the data sequence, see the Compressed Data Stream Definition section.
[31:0] Compressed Data Register, CDR[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined.
Interrupt Mask / Status Register
Direct (Read/Write) Register Byte Offset 0x0C
This 16-bit register contains interrupt mask and status bits that control the state of the ADV611/ADV612’s HIRQ pin. With the
seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR), select the con-
ditions that are ORed together to determine the output of the HIRQ pin.
Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are
sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the
condition coming true, they cannot be read or tested for stable level true conditions multiple times.
The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by
using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers.
[0] CCIR-656 Error in CCIR-656 data stream, CCIRER. This read only status bit indicates the following:
0 No CCIR-656 Error condition, reset value
1 Unrecoverable error in CCIR-656 data stream (missing sync codes)
[1] Statistics Ready, STATSR. This read only status bit indicates the following:
0 No Statistics Ready condition, reset value (STATS_R pin LO)
1 Statistics Ready for BW calculator (STATS_R pin HI)
[2] Last Code Read, LCODE. This read only status bit indicates the last compressed data word for field will be
retrieved from the FIFO on the next read from the host bus.
0 No Last Code condition, reset value (LCODE pin LO)
1 Next read retrieves last word for field in FIFO (LCODE pin HI)
[3] FIFO Service Request, FIFOSRQ. This read only status bit indicates the following:
0 No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)
1 FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)
[4] FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV611/ADV612’s
compressed data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted
until MERR indicates that the DRAM has also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0 No FIFO Error condition, reset value (FIFO_ERR pin LO)
1 FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
REV. 0
–11–

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