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PDF ADV601 Data sheet ( Hoja de datos )

Número de pieza ADV601
Descripción Low Cost Multiformat Video Codec
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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No Preview Available ! ADV601 Hoja de datos, Descripción, Manual

a
Low Cost
Multiformat Video Codec
ADV601
FEATURES
Precise Compressed Bit Rate Control
Field Independent Compression
Flexible Video Interface Supports All Common
Formats, Including CCIR-656
General Purpose 8-, 16- or 32-Bit Host Interface With
512 Deep 32-Bit FIFO
PERFORMANCE
Real-Time Compression Or Decompression of CCIR-601
And Square Pixel Video:
720 ؋ 288 @ 50 Fields/Sec — PAL
768 ؋ 288 @ 50 Fields/Sec — PAL
720 ؋ 243 @ 60 Fields/Sec — NTSC
640 ؋ 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less To 350:1
Visually Loss-Less Compression At 4:1 on Natural
Images (Typical)
APPLICATIONS
Nonlinear Video Editing
Video Capture Systems
Remote CCTV Surveillance
Digital Camcorders
Broadcast Quality Video Distribution Systems
Video Insertion Equipment
Image And Video Archival Systems
Digital Video Tape
High Quality Video Teleconferencing
GENERAL DESCRIPTION
The ADV601 is a very low cost, single chip, dedicated function,
all digital CMOS VLSI device capable of supporting visually
loss-less to 350:1 real-time compression and decompression of
CCIR-601 digital video at very high image quality levels. The
chip integrates glueless video and host interfaces with on-chip
SRAM to permit low part count, system level implementations
suitable for a broad range of applications.
The ADV601 is a video encoder/decoder optimized for real-time
compression and decompression of interlaced digital video. All
features of the ADV601 are designed to yield high performance
at a breakthrough systems-level cost. Additionally, the unique
sub-band coding architecture of the ADV601 offers you many
application-specific advantages. A review of the General Theory
of Operation and Applying the ADV601 sections will help you
get the most use out of the ADV601 in any given application.
The ADV601 accepts component digital video through the
Video Interface and outputs a compressed bit stream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV601 accepts a compressed bit stream through the Host
Interface and outputs component digital video through the
Video Interface. The host accesses all of the ADV601’s control
and status registers using the Host Interface. An optional Digital
Signal Processor (DSP) may be used for calculating quantiza-
tion Bin Widths (BW) (instead of the host); the ADV601 sends
current field statistics and receives Bin Width results as a packet
I/O over the DSP serial port interface. A generic fixed-point DSP
(for instance the ADSP-2105) is more than adequate for these
calculations. Figure 1 summarizes the basic function of the part.
FUNCTIONAL BLOCK DIAGRAM
(continued on page 2)
256K X 16-BIT DRAM
(FIELD STORE)
DSP
(OPTIONAL)
DIGITAL
COMPONENT
VIDEO I/O
DIGITAL
VIDEO I/O
PORT
DRAM
MANAGER
WAVELET
FILTERS,
DECIMATOR, &
INTERPOLATOR
SERIAL
PORT
ADAPTIVE
QUANTIZER
ADV601
LOW COST, MULTIFORMAT
VIDEO CODEC
RUN
LENGTH
CODER
HUFFMAN
CODER
HOST
I/O PORT
& FIFO
HOST
ON-CHIP
TRANSFORM
BUFFER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997

1 page




ADV601 pdf
ADV601
Figure 4. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts)
REV. 0
Figure 5. Modified Mallat Diagram of Image
–5–

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ADV601 arduino
ADV601
[4] FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV601’s compressed
data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until
MERR indicates that the DRAM is also overflowed. If this condition occurs during decode, the video output will be
corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode,
FIFOERR is asserted. This read only status bit indicates the following:
0 No FIFO Error condition, reset value (FIFO_ERR pin LO)
1 FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)
[5] FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode.
In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when
FIFOSTP is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely
be performed. This status bit indicates the following:
0 No FIFO Stop condition, reset value (FIFO_STP pin LO)
1 FIFO empty (encode) or full (decode) (FIFO_STP pin HI)
[6] Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can
be caused by a defective DRAM, the inability of the Host to keep up with the ADV601 compressed data stream, or bit errors in
the data stream. Note that the ADV601 recovers from this condition without host intervention.
0 No memory error condition, reset value
1 Memory error
[7] Reserved (always read/write zero)
[8] Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:
0 Disable CCIR-656 data error interrupt, reset value
1 Enable interrupt on error in CCIR-656 data
[9] Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:
0 Disable Statistics Ready interrupt, reset value
1 Enable interrupt on Statistics Ready
[10] Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:
0 Disable Last Code Read interrupt, reset value
1 Enable interrupt on Last Code Read from FIFO
[11] Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:
0 Disable FIFO Service Request interrupt, reset value
1 Enable interrupt on FIFO Service Request
[12] Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:
0 Disable FIFO Stop interrupt, reset value
1 Enable interrupt on FIFO Stop
[13] Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:
0 Disable FIFO Error interrupt, reset value
1 Enable interrupt on FIFO Error
[14] Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:
0 Disable memory error interrupt, reset value
1 Enable interrupt on memory error
[15] Reserved (always read/write zero)
Mode Control Register
Indirect (Write Only) Register Index 0x00
This register holds configuration data for the ADV601’s video interface format and controls several other video interface features.
For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:
[3:0] Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all
other values are reserved):
0x0 CCIR-656
0x2 MLTPX (Philips)
0x3 Philips, reset value
0x8 Gray Scale
[4] VCLK Output Divided by two, VCLK2. This bit controls the following:
0 Do not divide VCLK output (VCLKO = VCLK), reset value
1 Divide VCLK output by two (VCLKO = VCLK/2)
REV. 0
–11–

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